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| 1995 data sheet description the m pd70208h (v40hl) is a high-speed, low-power 16-/8-bit microprocessor based on the m pd70208 (v40 tm ) with 16-bit architecture, 8-bit data bus, and general-purpose peripheral functions. the m pd70216h (v50hl) is a high-speed, low-power 16-bit microprocessor based on the m pd70216 (v50 tm ) with 16- bit architecture, 16-bit data bus, and general-purpose peripheral functions. the v40hl and v50hl offer 20 mhz operation, and in addition to the conventional standby functions, also allows the clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. it is also capable of 3 v operation in addition to the previous 5 v operation, making it ideally suited to battery driven systems. details are given in the following manuals. be sure to read when carrying out design work. ? v40hl, v50hl users manual C hardware (u11610e) ? 16-bit v series tm users manual C instruction (u11301j: japanese version) features ? high-speed, low-power version of v40 and v50 ? high-performance cpu (v20 tm /v30 tm software compatible) ? minimum instruction execution time: 100 ns (20 mhz, 5 v) 200 ns (10 mhz, 3 v) ? memory addressing space: 1m bytes ? high-speed multiply/divide instructions: 0.95 to 2.8 m s (20 mhz, 5 v) 1.9 to 5.6 m s (10 mhz, 3 v) ? maskable (icu) & non-maskable (nmi) interrupt inputs ? m pd8080af emulation function ? standby functions, clock stoppage capability ? standard peripheral lsi functions on chip ? clock generator (cg) ? programmable wait control unit (wcu) ? refresh control unit (refu) ? timer/counter unit (tcu) m pd71054 subset ? serial control unit (scu) m pd71051 subset ? interrupt control unit (icu) m pd71059 subset ? dma control unit (dmau) m pd71071/71037 subset (functions of either selectable) ? operating frequency: 10/12.5/16/20 mhz (at 5 v, with 20/25/32/40 mhz supplied externally) 5/6.25/8/10 mhz (at 3 v, with 10/12.5/16/20 mhz supplied externally) v40hl tm , v50hl tm 16/8, 16-bit microprocessor mos integrated circuit m pd70208h, 70216h the mark shows the the major revised points. document no. u13225ej4v0ds00 (4th edition) date published april 1999 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd70208h, 70216h data sheet u13225ej4v0ds00 ordering information (1) v40hl max. operating part number package frequency (mhz) m pd70208hgf-10-3b9 80-pin plastic qfp (14 20 mm) 10 (resin thickness 2.7 mm) m pd70208hgf-12-3b9 80-pin plastic qfp (14 20 mm) 12.5 (resin thickness 2.7 mm) m pd70208hgf-16-3b9 80-pin plastic qfp (14 20 mm) 16 (resin thickness 2.7 mm) m pd70208hgf-20-3b9 80-pin plastic qfp (14 20 mm) 20 (resin thickness 2.7 mm) m pd70208hgk-10-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 10 (resin thickness 1.0 mm) m pd70208hgk-12-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 12.5 (resin thickness 1.0 mm) m pd70208hgk-16-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 16 (resin thickness 1.0 mm) m pd70208hgk-20-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 20 (resin thickness 1.0 mm) m pd70208hlp-10 68-pin plastic qfj (950 950 mil) 10 m pd70208hlp-12 68-pin plastic qfj (950 950 mil) 12.5 m pd70208hlp-16 68-pin plastic qfj (950 950 mil) 16 m pd70208hlp-20 68-pin plastic qfj (950 950 mil) 20 (2) v50hl max. operating part number package frequency (mhz) m pd70216hgf-10-3b9 80-pin plastic qfp (14 20 mm) 10 (resin thickness 2.7 mm) m pd70216hgf-12-3b9 80-pin plastic qfp (14 20 mm) 12.5 (resin thickness 2.7 mm) m pd70216hgf-16-3b9 80-pin plastic qfp (14 20 mm) 16 (resin thickness 2.7 mm) m pd70216hgf-20-3b9 80-pin plastic qfp (14 20 mm) 20 (resin thickness 2.7 mm) m pd70216hgk-10-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 10 (resin thickness 1.0 mm) m pd70216hgk-12-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 12.5 (resin thickness 1.0 mm) m pd70216hgk-16-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 16 (resin thickness 1.0 mm) m pd70216hgk-20-9eu 80-pin plastic tqfp (fine pitch) (12 12 mm) 20 (resin thickness 1.0 mm) m pd70216hlp-10 68-pin plastic qfj (950 950 mil) 10 m pd70216hlp-12 68-pin plastic qfj (950 950 mil) 12.5 m pd70216hlp-16 68-pin plastic qfj (950 950 mil) 16 m pd70216hlp-20 68-pin plastic qfj (950 950 mil) 20 3 m pd70208h, 70216h data sheet u13225ej4v0ds00 pin configuration (top view) (1) v40hl ? 80-pin plastic qfp (14 20 mm) m pd70208hgf-10-3b9 m pd70208hgf-12-3b9 m pd70208hgf-16-3b9 m pd70208hgf-20-3b9 caution leave ic pin open. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 a16/ps0 nc a15 a14 a13 a12 a11 a10 a9 a8 gnd nc gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 nc nc end/tc iord nc mwr iowr buslock bufr/w bufen clkout x1 x2 gnd nc gnd high astb qs0 qs1 poll tctl2 tout2 tclk nc intp7 intp6 a17/ps1 a18/ps2 a19/ps3 refrq hldrq hldak resout v dd v dd reset ready nmi bs2 bs1 bs0 mrd dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3/r x d dmaak3/t x d ic intak/srdy/tout1 v dd intp1 intp2 intp3 intp4 intp5 4 m pd70208h, 70216h data sheet u13225ej4v0ds00 ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd70208hgk-10-9eu m pd70208hgk-12-9eu m pd70208hgk-16-9eu m pd70208hgk-20-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 a15 nc a14 a13 a12 a11 a10 a9 a8 gnd gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 nc nc mwr iowr buslock bufr/w bufen clkout x1 x2 gnd gnd high astb qs0 qs1 poll tctl2 tout2 tclk nc nc a16/ps0 a17/ps1 a18/ps2 a19/ps3 refrq hldrq hldak resout v dd v dd reset ready nmi bs2 bs1 bs0 mrd iord nc nc end/tc dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3/r x d dmaak3/t x d intak/srdy/tout1 v dd intp1 intp2 intp3 intp4 intp5 intp6 intp7 nc 5 m pd70208h, 70216h data sheet u13225ej4v0ds00 ? 68-pin plastic qfj (950 950 mil) m pd70208hlp-10 m pd70208hlp-12 m pd70208hlp-16 m pd70208hlp-20 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a15 a14 a13 a12 a11 a10 a9 a8 gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 mwr iowr buslock bufr/w bufen clkout x1 x2 gnd high astb qs0 qs1 poll tctl2 tout2 tclk a16/ps0 a17/ps1 a18/ps2 a19/ps3 refrq hldrq hldak resout v dd reset ready nmi bs2 bs1 bs0 mrd iord end/tc dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3/r x d dmaak3/t x d intak/srdy/tout1 intp1 intp2 intp3 intp4 intp5 intp6 intp7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 6 m pd70208h, 70216h data sheet u13225ej4v0ds00 (2) v50hl ? 80-pin plastic qfp (14 20 mm) m pd70216hgf-10-3b9 m pd70216hgf-12-3b9 m pd70216hgf-16-3b9 m pd70216hgf-20-3b9 caution leave ic pin open. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 a16/ps0 nc ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 gnd nc gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 nc nc end/tc iord nc mwr iowr buslock bufr/w bufen clkout x1 x2 gnd nc gnd ube astb qs0 qs1 poll tctl2 tout2 tclk nc intp7 intp6 a17/ps1 a18/ps2 a19/ps3 refrq hldrq hldak resout v dd v dd reset ready nmi bs2 bs1 bs0 mrd dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3/r x d dmaak3/t x d ic intak/srdy/tout1 v dd intp1 intp2 intp3 intp4 intp5 7 m pd70208h, 70216h data sheet u13225ej4v0ds00 ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd70216hgk-10-9eu m pd70216hgk-12-9eu m pd70216hgk-16-9eu m pd70216hgk-20-9eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ad15 nc ad14 ad13 ad12 ad11 ad10 ad9 ad8 gnd gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 nc nc mwr iowr buslock bufr/w bufen clkout x1 x2 gnd gnd ube astb qs0 qs1 poll tctl2 tout2 tclk nc nc a16/ps0 a17/ps1 a18/ps2 a19/ps3 refrq hldrq hldak resout v dd v dd reset ready nmi bs2 bs1 bs0 mrd iord nc nc end/tc dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3/r x d dmaak3/t x d intak/srdy/tout1 v dd intp1 intp2 intp3 intp4 intp5 intp6 intp7 nc 8 m pd70208h, 70216h data sheet u13225ej4v0ds00 ? 68-pin plastic qfj (950 950 mil) m pd70216hlp-10 m pd70216hlp-12 m pd70216hlp-16 m pd70216hlp-20 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 gnd ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 mwr iowr buslock bufr/w bufen clkout x1 x2 gnd ube astb qs0 qs1 poll tctl2 tout2 tclk a16/ps0 a17/ps1 a18/ps2 a19/ps3 refrq hldrq hldak resout v dd reset ready nmi bs2 bs1 bs0 mrd iord end/tc dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3/r x d dmaak3/t x d intak/srdy/tout1 intp1 intp2 intp3 intp4 intp5 intp6 intp7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 9 m pd70208h, 70216h data sheet u13225ej4v0ds00 pin names a8-a15 : address bus a16/ps0-a19/ps3 : address/processor status ad0-ad15 : address bus/data bus astb : address strobe bs0-bs2 : bus status bufen : buffer enable bufr/w : buffer read/write buslock : bus lock clkout : clock output dmaak0-dmaak2 : dma acknowledge dmaak3/t x d : dma acknowledge/transmit data dmarq0-dmarq2 : dma request dmarq3/r x d : dma request/receive data end/tc : end/terminal count gnd : ground high : high level output hldak : hold acknowledge hldrq : hold request ic : internally connected intak/srdy/tout1 : interrupt acknowledge/serial ready/timer output 1 intp1-intp7 : interrupt request from peripherals iord : i/o read iowr : i/o write mrd : memory read mwr : memory write nc : no connection nmi : non-maskable interrupt request poll : poll qs0, qs1 : queue status ready : ready refrq : refresh request reset : reset resout : reset output tclk : timer clock tctl2 : timer control 2 tout2 : timer output 2 ube : upper byte enable v dd : power supply x1, x2 : crystal 10 m pd70208h, 70216h data sheet u13225ej4v0ds00 block diagram (1) v40hl cpu : central processing unit refu : reflesh control unit cg : clock generator tcu : timer/count unit biu : bus interface unit scu : serial control unit bau : bus arbitration unit icu : interrupt control unit wcu : wait control unit dmau : dma control unit tout2 tout1 tctl2 tclk intp7 intp6 intp5 intp4 intp3 intp2 intp1 intak nmi x2 x1 clkout dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3 dmaak3 end/tc refrq hldak hldrq poll buslock bufen bufr/w high astb iowr iord mwr mrd ready resout reset a16/ps0-a19/ps3 a8-a15 bs0-bs2 qs0 r x d srdy t x d tcu scu icu cpu wcu biu bau dmau refu cg ad0-ad7 qs1 11 m pd70208h, 70216h data sheet u13225ej4v0ds00 (2) v50hl tout2 tout1 tctl2 tclk intp7 intp6 intp5 intp4 intp3 intp2 intp1 intak nmi x2 x1 clkout dmarq0 dmaak0 dmarq1 dmaak1 dmarq2 dmaak2 dmarq3 dmaak3 end/tc refrq hldak hldrq poll buslock bufen bufr/w ube astb iowr iord mwr mrd ready resout reset a16/ps0-a19/ps3 ad0-ad15 bs0-bs2 qs1 qs0 r x d srdy t x d tcu scu icu cg dmau bau cpu refu wcu biu 12 m pd70208h, 70216h data sheet u13225ej4v0ds00 operating supply voltage v dd = 5 v v dd = 3 v internal i/o relocation function wait control unit (wcu) serial control unit (scu) dma control unit (dmau) standby functions 3 v, 5 v max. : 10, 12.5, 16, 20 mhz min. : dc max. : 5, 6.25, 8, 10 mhz min. : dc variable scaling factor variable instruction cycle time maximum input frequency: 40 mhz switchable 8-bit boundary or 16-bit boundary relocation function memory space: 5 divisions note 1 i/o space: 3 divisions note 2 refresh address: 16 bits refrq extended timing supported dedicated baud rate generator incorporated m pd71071/71037 subset (either function selectable) halt mode, stop mode 5 v max. : 8, 10 mhz min. : 2 mhz no operation fixed scaling factor fixed instruction cycle time maximum input frequency: 20 mhz v40: relocation possible on 8-bit boundary v50: relocation possible on 16-bit boundary memory space: 3 divisions i/o space: not divided refresh address: 9 bits no refrq extended timing no dedicated baund rate generator incorporated m pd71071 subset halt mode only differences from v40 and v50 item v40, v50 v40hl, v50hl refresh control unit (refu) clock generator (cg) operating frequency notes 1. divided into 3 when a reset is performed. 2. not divided when a reset is performed. 13 m pd70208h, 70216h data sheet u13225ej4v0ds00 contents 1. pin functions ............................................................................................................................... .... 15 1.1 list of pin functions ........................................................................................................................... 15 1.2 processing of unused pins .............................................................................................................. 17 2. memory and i/o configuration ................................................................................................ 19 2.1 memory space ............................................................................................................................... .......... 19 2.2 i/o space ............................................................................................................................... ..................... 21 3. cpu .......................................................................................................................... .............................. 22 4. cg (clock generator) ................................................................................................................. 24 5. biu (bus interface unit) .............................................................................................................. 24 6. bau (bus arbitration unit) ........................................................................................................ 25 7. wcu (wait control unit) ................................................................................................................ 27 7.1 features ............................................................................................................................... .................... 27 7.2 relation between wcu and ready pin ........................................................................................ 28 8. refu (refresh control unit) .................................................................................................... 29 8.1 features ............................................................................................................................... .................... 29 8.2 refresh operations ............................................................................................................................ 29 9. tcu (timer/counter unit) ............................................................................................................ 30 9.1 features ............................................................................................................................... .................... 30 9.2 tcu internal block diagram ........................................................................................................... 30 10. scu (serial control unit) .......................................................................................................... 31 10.1 features ............................................................................................................................... .................... 31 10.2 scu internal block diagram ........................................................................................................... 31 11. icu (interrupt control unit) .................................................................................................... 32 11.1 features ............................................................................................................................... .................... 32 11.2 icu internal block diagram ............................................................................................................ 32 12. dmau (dma control unit) ............................................................................................................ 33 12.1 features ............................................................................................................................... .................... 33 12.2 dmau internal block diagram ....................................................................................................... 33 13. standby functions ........................................................................................................................ 34 14. reset operation ............................................................................................................................. 34 15. instruction set ............................................................................................................................... 35 14 m pd70208h, 70216h data sheet u13225ej4v0ds00 16. electrical specifications ......................................................................................................... 66 16.1 at 5 v operation ............................................................................................................................... ..... 66 16.2 at 3 v operation ............................................................................................................................... ..... 75 17. package drawings ........................................................................................................................ 100 18. recommended soldering conditions ................................................................................... 103 15 m pd70208h, 70216h data sheet u13225ej4v0ds00 1. pin functions 1.1 list of pin functions pin name input/output function ad0 to ad15 note 1, 3 3-state i/o time-division address/data bus ad0 to ad7 note 2, 3 3-state i/o time-division address/data bus a8 to a15 note 2, 3 3-state output address bus a16/ps0 to a19/ps3 note 3 3-state output time-division address/processor status refrq output refresh request hldrq input bus hold request hldak output bus hold acknowledge reset input reset resout output system reset output ready input bus cycle end nmi input non-maskable interrupt mrd note 3 3-state output memory read strobe mwr note 3 3-state output memory read strobe iord note 3 3-state output i/o read strobe iowr note 3 3-state output i/o write strobe astb output address strobe ube note 1, 3 3-state output data bus upper byte enable high note 2 3-state output high level output buslock note 3 3-state output bus lock poll input floating-point operation processor polling bufr/w note 3 3-state output buffer read/write bufen note 3 3-state output buffer enable x1 input crystal/external clock x2 clkout output clock output bs0 to bs2 note 3 3-state output bus status qs0, qs1 output queue status tout2 output timer 2 output tctl2 input timer 2 control tclk input timer clock intp1 to intp7 input maskable interrupts intak/srdy/tout1 output interrupt acknowledge/serial reception ready/timer 1 output notes 1. v50hl only 2. v40hl only 3. these pins are provided with a latch. therefore, when they go into a high-impedance state, they hold the status before the high-impedance state until driven by an external device. it is not necessary to pull up or down the data bus. to invert the level of the pin that goes into a high-impedance state by an external device, a drive current higher than the latch invert current (i ilh , i ill ) is necessary. 16 m pd70208h, 70216h data sheet u13225ej4v0ds00 pin name input/output function dmaak3/t x d output dma acknowledge 3/serial transmit data dmarq3/r x d input dma request 3/serial receive data dmaak0 to dmaak2 output dma acknowledge dmarq0 to dmarq2 input dma request end/tc i/o dma service forcible termination/dma service completion v dd positive power supply pin gnd ground potential pin ic internal connection pin (external connection impossible) 17 m pd70208h, 70216h data sheet u13225ej4v0ds00 1.2 processing of unused pins table 1-1 shows the processing (recommended connection) of the unused pins. use of a resistor with a resistance of 1 to 10 k w is recommended to connect these pins to v dd or gnd via resistor. table 1-1. processing of unused pins pin name input/output recommended connection ad0 to ad15 note 1 3-state i/o open ad0 to ad7 note 2 3-state i/o a8 to a15 note 2 3-state output a16/ps0 to a19/ps3 3-state output refrq output hldrq input connect to gnd via resistor hldak output open resout output open ready input connect to v dd via resistor nmi input connect to gnd via resistor mrd 3-state output open mwr 3-state output iord 3-state output iowr 3-state output astb output ube note 1 3-state output high note 2 output buslock 3-state output poll input connect to gnd via resistor bufr/w 3-state output open bufen 3-state output clkout output open bs0 to bs2 3-state output qs0, qs1 output tout2 output tctl2 input connect to gnd via resistor tclk input intp1 to intp7 input open intak/srdy/tout1 output dmaak3/txd output dmarq3/rxd input connect to gnd via resistor dmaak0 to dmaak2 output open dmarq0 to dmarq2 input connect to gnd via resistor end/tc i/o individually connect to v dd via resistor notes 1. v50hl only 2. v40hl only 18 m pd70208h, 70216h data sheet u13225ej4v0ds00 remark the circuit configuration of the latch is as illustrated below. to invert the level of the pin with a latch, a drive current higher than the latch invert current is necessary. (1) output pin (2) i/o pin output buffer hi-z control latch output pin address bus, control bus output buffer hi-z control latch i/o pin (data bus) input buffer 19 m pd70208h, 70216h data sheet u13225ej4v0ds00 2. memory and i/o configuration 2.1 memory space the v40hl and v50hl can access a 1m-byte (512k-word) memory space. figure 2-1. memory map figure 2-2. interface with memory (1/2) (a) v40hl fffffh ffffch ffffbh ffff0h fffefh 00400h 003ffh 00000h reserved dedicated general use interrupt vector table d0-d7 a0-a19 data bus (8) memory 1m byte 8 address bus (20) 20 m pd70208h, 70216h data sheet u13225ej4v0ds00 figure 2-2. interface with memory (2/2) (b) v50hl d0-d15 a1-a19 data bus (16) memory lower bank 512k byte 8 memory upper bank 512k byte 8 address bus (19) a0 ube 19 19 d8-d15 d0-d7 bsel bsel 21 m pd70208h, 70216h data sheet u13225ej4v0ds00 2.2 i/o space in the v40hl and v50hl, i/os up to 64k bytes (32k words) can be accessed in an area independent of the memory. the various on-chip peripheral lsis are set by accessing the system i/o area. extended functions added to those of the v40 and v50 are mapped onto unused v40 and v50 registers and the reserved area. the i/o map is shown in figure 2-3. figure 2-3. i/o map dmau ffffh ffe0h ffdfh ff00h feffh 0000h 256 bytes icu tcu scu reserved area system i/o area area used for setting of i/o boundary, wcu, refu, baud rate generator, etc., and dmau, icu, tcu and scu allocation. the dmau, icu, tcu and scu are allocated within any 256 bytes. internal i/o area external i/o area 22 m pd70208h, 70216h data sheet u13225ej4v0ds00 3. cpu the cpu has the same functions as the v20hl tm and v30hl tm . in hardware terms, there are some changes regarding the use of the bus with on-chip peripherals, but in software terms the cpu is fully compatible. the internal block diagram of the cpu is shown in figure 3-1. figure 3-1. internal block diagram of cpu (1/2) (a) v40hl ps adm ss ds0 ds1 pfp dp temp q0 q2 q1 q3 lc pc aw bw cw dw ix iy bp sp tc ta tb shifter alu psw instruction decoder effective address generator 29 sub data bus (16) main data bus (16) queue data bus (8) micro data bus t-state control cycle decision queue control standby control interrupt control nmi int (from icu) clock (from cg) to biu bcu exu internal address/data bus (20) instruction rom address register m sequence control m m 23 m pd70208h, 70216h data sheet u13225ej4v0ds00 figure 3-1. internal block diagram of cpu (2/2) (b) v50hl ps adm ss ds0 ds1 pfp dp temp q0 q2 q1 q3 lc pc aw bw cw dw ix iy bp sp tc ta tb shifter alu psw instruction decoder effective address generator 29 sub data bus (16) main data bus (16) queue data bus (8) micro data bus t-state control cycle decision queue control standby control interrupt control nmi int (from icu) clock (from cg) to biu bcu exu internal address/data bus (20) q4 q5 instruction rom address register m sequence control m m 24 m pd70208h, 70216h data sheet u13225ej4v0ds00 4. cg (clock generator) the cg generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the x1 and x2 pins, supplies it as the cpu operating clock and outputs it externally as the clkout pin output. the interrupt cycle time can be changed according to the oscillator scaling factor. the scaling factor can be set by a system i/o area register. figure 4-1. internal block diagram of cg 5. biu (bus interface unit) the biu controls the data bus, address bus and control bus pins. these buses are used by the cpu, dmau (dma control unit) and refu (refresh control unit). the biu synchronizes the reset input signal and ready input signal using the clock signal generated by the clock generator (cg). in addition to being supplied to the inside of the v40hl and v50hl, the synchronized reset signal is also output externally from the resout pin. the synchronized ready signal is supplied to the internal cpu, dmau and refu. figure 5-1. reset and ready signal synchronization x1 x2 cpu, dmau, refu, scu clkout baud rate counter (brc) tcu oscillator divide-by-1-to-8 scaler divide-by-2-to-16 scaler divide-by-2 scaler f xx f x q d ck - q d ck q d ck reset ready clock resout to internal units to internal units 25 m pd70208h, 70216h data sheet u13225ej4v0ds00 6. bau (bus arbitration unit) the bau performs bus arbitration among bus masters. a list of bus masters (units which can acquire the bus) is shown below. table 6-1. bus masters bus master bus cycle cpu dmau refu external bus master (hldrq pin input) program fetch, data read/write dma cycle refresh cycle bus cycle driven by external device the relative priorities of the bus masters are shown below. high cpu (when buslock prefix is used) refu (highest priority: when given number of requests are reached) dmau hldrq pin cpu (normal cpu cycle) low refu (lowest priority: cycle steal) bau bus arbitration is performed as follows. a bus master such as the cpu, dmau, refu, etc., incorporated in the v40hl and v50hl normally release the bus at the end of the bus cycle currently being executed, as shown in figure 6-1. however, in the case of a bus master connected to the hldrq pin, or cascaded external dma controllers, for instance, the situation is as shown in figure 6-2. the v40hl and v50hl request return of the bus by inactivating the acknowledge signal (hldak), and on receiving this request, the external bus master holding the bus should release the bus by dropping the bus hold request signal (hldrq). the v40hl and v50hl-internal bus master with the highest priority is kept waiting until the bus hold request signal is dropped. this is called a bus wait operation. 26 m pd70208h, 70216h data sheet u13225ej4v0ds00 figure 6-1. internal bus cycles figure 6-2. bus wait operation note the period in which the external bus master which has been given the bus after its release by the v40hl and v50hl can use the bus. cpu cpu dma refresh refresh refresh bus cycle internal dma request internal refresh request (highest priority) bus wait bus release refresh note bus cycle hldrq pin hldak pin internal refresh request (highest priority) 27 m pd70208h, 70216h data sheet u13225ej4v0ds00 7. wcu (wait control unit) the wcu has the function of automatically inserting a wait state (tw) of 0 to 3 clock cycles in a cpu, dmau or refu bus cycle. 7.1 features ? automatic setting of 0 to 3 waits for a cpu memory bus cycle ? 1m-byte memory space can be divided into 5 ? 64k-byte i/o space can be divided into 3 ? automatic setting of 0 to 3 waits for an external i/o cycle ? automatic setting of 0 to 3 waits for a dma cycle ? automatic setting of 0 to 3 waits for a refresh cycle ? same as v40 and v50 directly after a reset (memory space divided into 3, no division of i/o space) figure 7-1. example of memory space division remark the division specification and the size of each block are set by means of a system i/o area register. fffffh 00000h 1 m-byte memory area upper memory block middle memory block lower memory block lower sub memory block upper sub memory block 28 m pd70208h, 70216h data sheet u13225ej4v0ds00 figure 7-2. example of i/o space division remark the division specification and the size of each block are set by means of a system i/o area register. 7.2 relation between wcu and ready pin when wait cycles exceeding 3 clock cycles are necessary, the wcu and the ready signal pin can be used in combination. the number of wait cycles specified by the wcu set value or the number of wait cycles under ready control, whichever is larger, is inserted. figure 7-3. wcu and ready control ffffh 0000h upper i/o block middle i/o block lower i/o block 64k-byte i/o area ready wcu bus control v40hl/v50hl 29 m pd70208h, 70216h data sheet u13225ej4v0ds00 8. refu (refresh control unit) the refu generates refresh cycles required for refreshing of external dram. refresh enabling/disabling and the refresh interval can be set programmably. 8.1 features ? lowest-priority refreshing/highest-priority refreshing ? 7-refresh queue ? 16-bit refresh address ? refrq extended timing supported (refrq active from t1 state) 8.2 refresh operations the refu has two priorities. normally, it has the lowest priority, and a refresh cycle cannot be started unless the bus is completely idle. however, if there are 7 or more pending refresh requests, it is given the highest priority, and it requests the bus master holding the bus to relinquish it. (see 6. bau .) the refresh address is output on a0 to a15. every refresh cycle the refresh address is incremented by 1 (for the v40hl) or by 2 (for the v50hl), and the next refresh address is generated. in a refresh cycle, a low-level signal is output on the low address pins (a16 to a19). this refresh address is not affected by a reset. when the device is powered on, the refresh address is undefined. 30 m pd70208h, 70216h data sheet u13225ej4v0ds00 9. tcu (timer/counter unit) the tcu incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. functionally it is a subset of the m pd71054. 9.1 features ? 3 16-bit counters ? six programmable count modes ? binary/bcd count ? multiple latch command ? choice of two input clocks: internal/external 9.2 tcu internal block diagram notes 1. a0 or a1 (set by a system i/o area register) 2. a1 or a2 (set by a system i/o area register) iord iowr note 1 tcu selection signal read/write control tmd (mode register) tclk (external) clock tctl0=high tout0 (to intl0) tctl1=high tout1 (external ) tctl2 (external) tout2 (external) to intl2/scu sw sw sw prescaler tct #0 status register status latch h(8) l(8) count register h(8) l(8) count latch tct #1 tct #2 down counter (16) control logic (16) (8) (16) (8) (8) (8) internal data bus note 2 31 m pd70208h, 70216h data sheet u13225ej4v0ds00 10. scu (serial control unit) the scu performs control of serial communication (asynchronous). its functions are a subset of the m pd71051 excluding synchronous communication. also, what was the control word register in the m pd71051 has been divided into two: a command register and a mode register. 10.1 features ? dedicated baud rate generator incorporated (using internal clock) ? asynchronous serial communication ? clock rate: baud rate 16, 64 ? baud rate: dc C 500 kbps ? character length: 7/8 bits ? transmit stop bits: 1/2 bits ? break transmission ? automatic break detection ? full-duplex double-buffer system ? parity addition/checking ? error detection: parity, overrun, framing ? interrupt generation maskable 10.2 scu internal block diagram notes 1. a0 or a1 (set by a system i/o area register) 2. a1 or a2 (set by a system i/o area register) internal data bus sst status register scm command register srb receive data buffer stb transmit data buffer smd mode register simk interrupt mask register (8) (8) scu status control bus baud rate generator read/write control from cg receiver (including receive buffer) transmitter (including transmit buffer) interrupt generation logic selector from tcu (tout1 output) iord iowr note 1 scu selection signal srdy (external) r x d (external) t x d (external) rtclk sint (to intl1) reset clock note 2 32 m pd70208h, 70216h data sheet u13225ej4v0ds00 11. icu (interrupt control unit) the icu arbitrates among up to 8 interrupt requests (maskable interrupts) generated inside and outside the v40hl and v50hl, and transfers one of them to the cpu. the icu functions comprise the functions of the v40hl and v50hl minus those functions not required by the v40hl and v50hl. 11.1 features ? 8 interrupt inputs ? m pd71059 cascading possible ? edge- or level-triggered request input (input from internally connected tcu is edge-triggered only) ? interrupt requests individually maskable ? programmable interrupt request priority order ? polling operation capability 11.2 icu internal block diagram notes 1. a0 or a1 (set by a system i/o area register) 2. a1 or a2 (set by a system i/o area register) iord iowr icu selection signal read/write control initialize & command word register group slave control control logic interrupt in-service register (iis) priority determina- tion logic interrupt mask register (imk) interrupt request register (irq) external pins internal data bus sa0 sa1 sa2 a8 a9 a10 intp1 intp2 intp3 intp4 intp5 intp6 intp7 intl1 intl2 intl3 intl4 intl5 intl6 intl7 intl0 to biu intak (from cpu) int (to cpu) tout0 (from tcu) sint (from scu) tout1 (from tcu) sw sw note 1 note 2 33 m pd70208h, 70216h data sheet u13225ej4v0ds00 12. dmau (dma control unit) the dmau has 4 dma channels, and provides the functions (subset) of two lsis, the m pd71071 and m pd71037. 12.1 features ? two operating modes ( m pd71071 mode, m pd71037 mode) ? 20-bit address register ? 16-bit count register ? four independent dma channels ? byte transfer/word transfer selectable ? three transfer modes (settable on an individual channel basis) single transfer mode, demand transfer mode, block transfer mode ? two bus modes (common to all channels: in m pd71037 mode, bus release mode only) bus release mode bus hold mode ? dma requests maskable on an individual channel basis ? auto initialization function ? transfer address increment/decrement ? two channel priority systems (fixed priority/rotating priority) ? tc output at end of transfer ? forced termination of service by end input ? cascading capability 12.2 dmau internal block diagram notes 1. in m pd71071 mode 2. in m pd71037 mode (20) (8) internal address bus internal data bus internal control bus busrq busak bau dmarq0- dmarq3 dmaak0- dmaak3 external pins end/tc internal bus interface priority control dmau address bus (20) address increment/ decrement (20) address registers current address (20 4) base address (20 4) dmau data bus count registers base count (16 4) current count (16 4) terminal count count decrementer (16) control register group channel note 1 (4) device control (10) status (8) mode control (7 4) mask (4) request (4) note 2 34 m pd70208h, 70216h data sheet u13225ej4v0ds00 13. standby functions the v40hl and v50hl have two modes, the halt mode and stop mode, as standby functions. (1) halt mode when the halt instruction is executed, the clock to internal cpu circuitry (excluding the halt mode release circuit) is stopped. (2) stop mode when the halt instruction is executed, all clocks to the cpu and internal i/os are stopped. stop mode should be used when a resonator is connected to the x1 and x2 pins. remark switching between halt mode and stop mode is performed by setting a system i/o area register. 14. reset operation when the reset pin is driven low and this level is held for 4 clock cycles or more from the fall of the signal, the cpu and on-chip peripheral lsis are reset. when the reset pin subsequently returns to the high level, the cpu begins an instruction prefetch from address ffff0h. when the v40hl and v50hl are reset, its status is fully compatible with the v40 and v50. extended functions added to those of the v40 and v50 are mapped onto unused v40 and v50 registers and the reserved area. table 14-1 shows the main statuses of the on-chip peripheral lsis when a reset is performed. table 14-1. main statuses of on-chip peripheral lsis after reset memory, external i/o, dma & refresh : 3-wait insertion upper & lower memory blocks : set to 512 kb refresh cycle : set to 72 clock cycles refresh enabling/disabling : not affected by reset baud rate : x 64 character : 7 bits parity : none stop bits : 1 bit break detection : none m pd71071 mode demand mode auto initialization disabled verify transfer, byte transfer bus release mode dma enabled dmau scu refu wcu caution when a reset is performed, the scu, tcu, icu and dmau cannot be used. 35 m pd70208h, 70216h data sheet u13225ej4v0ds00 15. instruction set table 15-1. operand type legend description reg reg reg8 reg8 reg16 reg16 dmem mem mem8 mem16 mem32 imm imm3 imm4 imm8 imm16 acc sreg src-table src-block dst-block near-proc far-proc near-label short-label far-label memptr16 memptr32 regptr16 pop-value fp-op r 8/16-bit general register (destination register in an instruction using two 8/16-bit general registers) source register in an instruction using two 8/16-bit general registers 8-bit general register (destination register in an instruction using two 8-bit general registers) source register in an instruction using two 8-bit general registers 16-bit general register (destination register in an instruction using two 16-bit general registers) source register in an instruction using two 16-bit general registers 8/16-bit memory location 8/16-bit memory location 8-bit memory location 16-bit memory location 32-bit memory location constant in range 0 to ffffh constant in range 0 to 7 constant in range 0 to fh constant in range 0 to ffh constant in range 0 to ffffh accumulator aw or al segment register name of 256-byte conversion translation table name of block addressed by register ix name of block addressed by register iy procedure in current program segment procedure in a different program segment label in current program segment label in range C128 to +127 bytes from end of instruction label in a different program segment word containing location offset in a different program segment to which control is to be shifted and segment base address doubleword containing location offset in a different program segment to which control is to be shifted and segment base address general register containing location offset in a different program segment to which control is to be shifted number of bytes to be removed from stack (0 to 64k, normally an even number) immediate value which identifies external floating-point operation coprocessor operation code register set identifier 36 m pd70208h, 70216h data sheet u13225ej4v0ds00 table 15-2. operation code legend identifier description w reg reg mem mod s x, xxx, yyy, zzz byte/word specification bit (0: byte, 1: word). however, when s =1, byte data of sign extension is 16-bit operand if w = 1. register field (000 to 111) register field (000 to 111) (source register in instruction which uses two registers) memory field (000 to 111) mode field (00 to 10) sign-extended specification bit (0: without sign extension, 1: with sign extension) data used to determine external floating-point coprocessor operation code 37 m pd70208h, 70216h data sheet u13225ej4v0ds00 accumulator (16-bit) accumulator (high-order byte) accumulator (low-order byte) register bw (16-bit) register cw (16-bit) register cl (low-order byte) register dw (16-bit) base pointer (16-bit) stack pointer (16-bit) program counter (16-bit) program status word (16-bit) index register (source) (16-bit) index register (destination) (16-bit) program segment register (16-bit) stack segment register (16-bit) data segment 0 register (16-bit) data segment 1 register (16-bit) auxiliary carry flag carry flag parity flag sign flag zero flag direction flag interrupt enable flag overflow flag break flag mode flag contents of memory indicated by contents of ( ) displacement (8/16-bit) 16 bits with 8-bit displacement sign-extended temporary register (8/16/32-bit) temporary register a (16-bit) temporary register b (16-bit) temporary register c (16-bit) temporary carry flag (1-bit) immediate segment data (16-bit) immediate offset data (16-bit) transfer direction addition subtraction multiplication division modulo logical product logical sum exclusive logical sum two-digit hexadecimal number four-digit hexadecimal number table 15-3. operand description legend description identifier aw ah al bw cw cl dw bp sp pc psw ix iy ps ss ds0 ds1 ac cy p s z dir ie v brk md ( ... ) disp ext-disp8 temp ta tb tc tmpcy seg offset ? + C ? % h h 38 m pd70208h, 70216h data sheet u13225ej4v0ds00 table 15-4. flag operation legend identifier description (blank) no change 0 cleared to 0 1 set to 1 set or cleared depending upon result u undefined r previously saved value is restored mod mem 00 000 001 010 011 100 101 110 111 bw + ix bw + iy bp + ix bp + iy ix iy direct address bw bw + ix + disp 8 bw + iy + disp 8 bp + ix + disp 8 bp + iy + disp 8 ix + disp 8 iy + disp 8 bp + disp 8 bw + disp 8 bw + ix + disp 16 bw + iy + disp 16 bp + ix + disp 16 bp + iy + disp 16 ix + disp 16 iy + disp 16 bp + disp 16 bw + disp 16 table 15-5. memory addressing 01 10 table 15-6. 8/16-bit general register selection reg, reg w=0 w=1 000 al aw 001 cl cw 010 dl dw 011 bl bw 100 ah sp 101 ch bp 110 dh ix 111 bh iy table 15-7. segment register selection sreg 00 ds1 01 ps 10 ss 11 ds0 39 m pd70208h, 70216h data sheet u13225ej4v0ds00 the instruction set is shown in tabular form on the following pages. clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the following conditions. ? prefetch time and wait time for using bus, etc. are not included. ? 0 wait is assumed for memory access. that is, the clock number of one bus cycle is four clock cycle. ? 0 wait is assumed for i/o access. ? primitive block transfer instruction and primitive input/output instruction is included repeat prefixes. the number of clock cycle of instruction with byte processing and word processing (with w bit) is shown as the followings. (1) v40hl on the left of "/" : the value corresponding to byte processing (w= 0) or word processing (w = 1) of even address on the right of "/": the value corresponding to word processing (w =1) of odd address for the clock of block transfer related instruction of v40hl, see table 15-8 . table 15-8. number of clock cycles in block transfer related instruction (v40hl) instruction number of clock cycles byte processing (w = 0) word processing (w = 1) movbk 9 + 8 rep 9 + 16 rep (9) (17) cmpbk 7 + 14 rep 7 + 22 rep (13) (21) cmpm 7 + 10 rep 7 + 14 rep (7) (11) ldm 7 + 9 rep 7 + 13 rep (7) (11) stm 5 + 4 rep 5 + 8 rep (5) (9) inm 9 + 8 rep 9 + 16 rep (10) (18) outm 9 + 8 rep 9 + 16 rep (10) (18) remark the figures in parentheses apply to one-time processing only. 40 m pd70208h, 70216h data sheet u13225ej4v0ds00 (2) v50hl on the left of "/" : the value corresponding to byte processing (w= 0) or word processing (w = 1) of even address on the right of "/" : the value corresponding to word processing (w =1) of odd address for the clock of block transfer related instruction of v50hl, see table 15-9 . table 15-9. number of clock cycles in block transfer related instruction v50hl (1/2) number of clock cycles instruction byte processing word processing (w = 1) (w = 0) odd/odd address odd/even address even/even address movbk 9 + 8 rep 9 + 16 rep 9 + 12 rep 9 + 8 rep (9) (17) (13) (9) cmpbk 7 + 14 rep 7 + 22 rep 7 + 18 rep 7 + 14 rep (13) (21) (17) (13) inm 9 + 8 rep 9 + 16 rep 9 + 12 rep 9 + 8 rep (10) (18) (14) (10) outm 9 + 8 rep 9 + 16 rep 9 + 12 rep 9 + 8 rep (10) (18) (14) (10) remark the figures in parentheses apply to one-time processing only. table 15-9. number of clock cycles in block transfer related instruction (v50hl) (2/2) number of clock cycles instruction byte processing word processing (w = 1) (w = 0) odd address even address cmpm 7 + 10 rep 7 + 14 rep 7 + 10 rep (7) (11) (7) ldm 7 + 9 rep 7 + 13 rep 7 + 9 rep (7) (11) (7) stm 5 + 4 rep 5 + 8 rep 5 + 4 rep (5) (9) (5) remark the figures in parentheses apply to one-time processing only. 41 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group data transfer instructions mnemonic operand(s) operation operation code flags 76543210 76543210 clock cycles reg ? reg (mem) ? reg reg ? (mem) (mem) ? imm reg ? imm if w=0: al ? (dmem) if w=1: ah ? (dmem + 1), al ? (dmem) if w=0: (dmem) ? al if w=1: (dmem + 1) ? ah, (dmem) ? al sreg ? reg16 sreg:ss, ds0, ds1 sreg ? (mem16) sreg:ss, ds0, ds1 reg16 ? sreg (mem16) ? sreg reg16 ? (mem32) ds0 ? (mem32 + 2) reg16 ? (mem32) ds1 ? (mem32 + 2) ah ? s, z, , ac, , p, , cy s, z, , ac, , p, , cy ? ah reg16 ? mem16 al ? (bw + al) reg ? reg (mem) ? reg aw ? reg16 mov reg, reg mem, reg reg, mem mem, imm reg, imm acc, dmem dmem, acc sreg, reg16 sreg, mem16 reg16, sreg mem16, sreg ds0, reg16, mem32 ds1, reg16, mem32 ah, psw psw, ah reg16, mem16 src-table reg, reg mem, reg reg, mem aw, reg16 reg16, aw 1000101w 1000100w 1000101w 1100011w 1011w reg 1010000w 1010001w 1000111 0 1000111 0 1000110 0 1000110 0 1100010 1 1100010 0 1001111 1 1001111 0 1000110 1 1101011 1 1000011w 1000011w 10010 reg 11 reg reg mod reg mem mod reg mem mod 000mem 110 sreg reg mod 0 sreg mem 110 sreg reg mod 0 sreg mem mod reg mem mod reg mem mod reg mem 1 1 reg reg mod reg mem 2 2-4 2-4 3-6 2-3 3 3 2 2-4 2 2-4 2-4 2-4 1 1 2-4 1 2 2-4 1 2 7/11 10/14 9/13 4 10/14 9/13 2 14 2 12 25 25 2 3 4 9 3 13/21 3 xch trans ldea bytes 2 7/11 10/14 9/13 4 10/14 9/13 2 10/14 2 8/12 17/25 17/25 2 3 4 9 3 13/21 3 v40hl v50hl 42 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 01100101 01100100 11110011 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 1 1 1 1 1 1 1 1 1 76543210 2 2 2 2 see table 15-8 see table 15-8 see table 15-8 see table 15-8 see table 15-8 repeat prefixes primitive block transfer instructions repc repnc rep repe repz repne repnz movbk cmpbk cmpm ldm stm dst-block, src-block src-block, dst-block dst-block src-block dst-block clock cycles 2 2 2 2 see table 15-9 see table 15-9 see table 15-9 see table 15-9 see table 15-9 v40hl v50hl while cw 1 0, the following byte primitive block transfer instruction is executed and cw is decremented (C1). if there is a pending interrupt, it is serviced. if cy 1 1 the loop is exited. same as above if cy 1 0 the loop is exited. while cw 1 0, the following byte primitive block transfer instruction is executed and cw is decremented (C1). if there is a pending interrupt, it is serviced. if the primitive block transfer instruction is cmpbk or cmpm and z 1 1 the loop is exited. same as above if z 1 0 the loop is exited. if w = 0: (iy) ? (ix) dir = 0 : ix ? ix + 1, iy ? iy + 1 dir = 1 : ix ? ix C 1, iy ? iy C 1 if w = 1: (iy + 1, iy) ? (ix + 1, ix) dir = 0 : ix ? ix + 2, iy ? iy + 2 dir = 1 : ix ? ix C 2, iy ? iy C 2 if w = 0: (ix) C (iy) dir = 0 : ix ? ix + 1, iy ? iy + 1 dir = 1 : ix ? ix C 1, iy ? iy C 1 if w = 1: (ix + 1, ix) C (iy + 1, iy) dir = 0 : ix ? ix + 2, iy ? iy + 2 dir = 1 : ix ? ix C 2, iy ? iy C 2 if w = 0: al C (iy) dir = 0 : iy ? iy + 1; dir = 1 : iy ? iy C 1 if w = 1: aw C (iy + 1, iy) dir = 0 : iy ? iy + 2; dir = 1 : iy ? iy C 2 if w = 0: al ? (ix) dir = 0 : ix ? ix + 1; dir = 1 : ix ? ix C 1 if w = 1: aw ? (ix + 1, ix) dir = 0 : ix + 2; dir = 1 : ix ? ix C 2 if w = 0: (iy) ? al dir = 0 : iy ? iy + 1; dir = 1 : iy ? iy C 1 if w = 1: (iy + 1, iy) ? aw dir = 0 : iy ? iy + 2; dir = 1 : iy ? iy C 2 43 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 00001111 1 1 reg reg 00001111 11000 reg 00001111 1 1 reg reg 00001111 11000 reg 1110010w 1110110w 1110011w 1110111w 0110110w 0110111w 3 4 3 4 2 1 2 1 1 1 76543210 16-bit field ? aw 16-bit field ? aw aw ? 16-bit field aw ? 16-bit field if w = 0: al ? (imm8) if w = 1: ah ? (imm8 + 1), al ? (imm8) if w = 0: al ? (dw) if w = 1: ah ? (dw + 1), al ? (dw) if w = 0: (imm8) ? al if w = 1: (imm8 + 1) ? ah, (imm8) ? al if w = 0: (dw) ? al if w = 1: (dw + 1) ? ah, (dw) ? al if w = 0: (iy) ? (dw) dir = 0 : iy ? iy + 1 ; dir = 1 : iy ? iy C 1 if w = 1: (iy + 1, iy) ? (dw + 1, dw) dir = 0 : iy ? iy + 2 ; dir = 1 : iy ? iy C 2 if w = 0: (dw) ? (ix ) dir = 0 : ix ? ix + 1 ; dir = 1 : ix ? ix C 1 if w = 1: (dw + 1, dw) ? (ix + 1, ix) dir = 0 : ix ? ix + 2 ; dir = 1 : ix ? ix C 2 35-133 35-133 34-59 34-59 9/13 8/12 8/12 8/12 see table 15-8 see table 15-8 ins ext in out inm outm 00110001 00111001 00110011 00111011 reg8, reg8 reg8, imm4 reg8, reg8 reg8, imm4 acc, imm8 acc, dw imm8, acc dw, acc dst-block, dw dw, src-block input/output instructions primitive input/output instructions bit field manipulation instructions note in case of in/out instruction to internal dmau, the number of word processing clock cycles applied is always that to the right of "/". clock cycles v40hl v50hl 31-117/ 35-133 31-117/ 35-133 26-55/ 34-59 26-55/ 34-59 9/13 note 8/12 note 8/12 note 8/12 note see table 15-9 see table 15-9 44 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) operation operation code flags 76543210 76543210 reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm 0000001w 0000000w 0000001w 100000sw 100000sw 0000010w 0001001w 0001000w 0001001w 100000s w 100000sw 0001010w 0010101w 0010100w 0010101w 100000sw 100000sw 0010110w 0001101w 0001100w 0001101w 100000sw 100000sw 0001110w 1 1 reg reg mod reg mem mod reg mem 11000 reg mod 000 mem 1 1 reg reg mod reg mem mod reg mem 11010 reg mod 010 mem 1 1 reg reg mod reg mem mod reg mem 11101 reg mod 101 mem 1 1 reg reg mod reg mem mod reg mem 11011 reg mod 011 mem 2 2-4 2-4 3-4 3-6 2-3 2 2-4 2-4 3-4 3-6 2-3 2 2-4 2-4 3-4 3-6 2-3 2 2-4 2-4 3-4 3-6 2-3 reg ? reg + reg (mem) ? (mem) + reg reg ? reg + (mem) reg ? reg + imm (mem) ? (mem) + imm if w = 0: al ? al + imm if w = 1: aw ? aw + imm reg ? reg + reg+ cy (mem) ? (mem) + reg + cy reg ? reg + (mem) + cy reg ? reg + imm + cy (mem) ? (mem) + imm + cy if w = 0: al ? al + imm + cy if w = 1: aw ? aw + imm + cy reg ? reg C reg (mem) ? (mem) C reg reg ? reg C (mem) reg ? reg C imm (mem) ? (mem) C imm if w = 0: al ? al C imm if w = 1: aw ? aw C imm reg ? reg C regC cy (mem) ? (mem) C reg C cy reg ? reg C (mem) C cy reg ? reg C imm C cy (mem) ? (mem) C imm C cy if w = 0: al ? al C imm C cy if w = 1: aw ? aw immC cy 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 add addc sub subc addition/subtraction instructions bytes clock cycles v40hl v50hl 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 45 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z u uuu u uuu u uuu dst bcd string ? dst bcd string + src bcd string * dst bcd string ? dst bcd string C src bcd string * dst bcd string C src bcd string * reg8 ? reg8 + 1 (mem) ? (mem) + 1 reg16 ? reg16 + 1 reg8 ? reg8 C 1 (mem) ? (mem) C 1 reg16 ? reg16 C 1 2 2 2 3 3-5 3 3-5 2 2-4 1 2 2-4 1 19 n + 7 19 n + 7 19 n + 7 13 25 17 29 2 13/21 2 2 13/21 2 00001111 00001111 00001111 00001111 11000 reg 00001111 mod 000 mem 00001111 11000 reg 00001111 mod 000 mem 11111110 1111111w 01000 reg 11111110 1111111w 01001 reg reg8 mem8 reg8 mem8 reg8 mem reg16 reg8 mem reg16 instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 76543210 add4s sub4s cmp4s rol4 ror4 inc dec 00100000 00100010 00100110 00101000 00101000 00101010 00101010 11000 reg mod 000 mem 11001 reg mod 001 mem bcd operation instructions increment/decre- ment instructions n: 1/2 the number of bcd digits * the number of bcd digits is given by the cl register: a value between 1 and 254 can be set. clock cycles v40hl 19 n + 7 19 n + 7 19 n + 7 13 25 17 29 2 13/21 2 2 13/21 2 v50hl upper lower upper al l reg upper al l lower mem upper al l lower reg al l mem lower 46 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) operation operation code flags 76543210 76543210 reg8 mem8 reg16 mem16 reg8 mem8 reg16 mem16 reg16, (reg16,) note imm8 reg16, mem16, imm8 reg16, (reg16,) note imm16 reg16, mem16, imm16 11110110 11110110 11110111 11110111 11110110 11110110 11110111 11110111 01101011 01101011 01101001 01101001 1110 0 reg mod 100 mem 1110 0 reg mod 100 mem 1110 1 reg mod 10 1 mem 1110 1 reg mod 10 1 mem 1 1 reg reg mod reg mem 1 1 reg reg mod reg mem 2 2-4 2 2-4 2 2-4 2 2-4 3 3-5 4 4-6 u uuu u uuu u uuu u uuu u uuu u uuu u uuu u uuu u uuu u uuu u uuu u uuu aw ? al reg8 ah = 0: cy ? 0, v ? 0 ah 1 0: cy ? 1, v ? 1 aw ? al (mem8) ah = 0: cy ? 0, v ? 0 ah 1 0: cy ? 1, v ? 1 dw, aw ? aw reg16 dw = 0: cy ? 0, v ? 0 dw 1 0: cy ? 1, v ? 1 dw, aw ? aw (mem16) dw = 0: cy ? 0, v ? 0 dw 1 0: cy ? 1, v ? 1 aw ? al reg8 ah = al sign extension: cy ? 0, v ? 0 ah 1 al sign extension: cy ? 1, v ? 1 aw ? al (mem8) ah = al sign extension: cy ? 0, v ? 0 ah 1 al sign extension: cy ? 1, v ? 1 dw, aw ? aw reg16 dw = aw sign extension: cy ? 0, v ? 0 dw 1 aw sign extension: cy ? 1, v ? 1 dw, aw ? aw (mem16) dw = aw sign extension: cy ? 0, v ? 0 dw 1 aw sign extension: cy ? 1, v ? 1 reg16 ? reg16 imm8 product 16 bits : cy ? 0, v ? 0 product > 16 bits : cy ? 1, v ? 1 reg16 ? (mem16) imm8 product 16 bits : cy ? 0, v ? 0 product > 16 bits : cy ? 1, v ? 1 reg16 ? reg16 imm16 product 16 bits : cy ? 0, v ? 0 product > 16 bits : cy ? 1, v ? 1 reg16 ? (mem16) imm16 product 16 bits : cy ? 0, v ? 0 product > 16 bits : cy ? 1, v ? 1 21-22 26-27 29-30 38-39 33-39 38-44 41-47 50-56 28-34 37-43 36-42 45-51 mulu mul multiplication instructions note the 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified. bytes clock cycles v40hl v50hl 21-22 26-27 29-30 34-35/ 38-39 33-39 38-44 41-47 46-52/ 50-56 28-34 33-39/ 37-43 36-42 41-47/ 45-51 47 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 76543210 reg8 mem8 reg16 mem16 11110110 11110110 11110111 11110111 11110 reg mod 110 mem 11110 reg mod 110 mem 2 2-4 2 2-4 uuuuuu uuuuuu uuuuuu uuuuuu temp ? aw if temp ? reg8 ffh ah ? temp%reg8, al ? temp ? reg8 if temp ? reg8 > ffh ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta temp ? aw if temp ? (mem8) ffh ah ? temp%(mem8), al ? temp ? (mem8) if temp ? (mem8) > ffh ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta temp ? dw, aw if temp ? reg16 ffffh dw ? temp%reg16, aw ? temp ? reg16 if temp ? reg16 > ffffh ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta temp ? dw, aw if temp ? (mem16) ffffh dw ? temp%(mem16), aw ? temp ? (mem16) if temp ? (mem16) > ffffh ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta 19 24 25 34 divu unsigned division instructions clock cycles v40hl v50hl 19 24 25 30/34 48 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 76543210 reg8 mem8 reg16 mem16 11110110 11110110 11110111 11110111 11111 reg mod 111 mem 11111 reg mod 111 mem 2 2-4 2 2-4 uuuuuu uuuuuu uuuuuu uuuuuu temp ? aw if temp ? reg8 > 0 and temp ? reg8 7fh or temp ? reg8 < 0 and temp ? reg8 > 0 C 7fh C1 ah ? temp%reg8, al ? temp ? reg8 if temp ? reg8 > 0 and temp ? reg8 > 7fh or temp ? reg8 < 0 and temp ? reg8 0 C 7fh C1 ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta temp ? aw if temp ? (mem8) > 0 and temp ? (mem8) 7fh or temp ? (mem8) < 0 and temp ? (mem8) > 0 C 7fh C1 ah ? temp%(mem8), al ? temp ? (mem8) if temp ? (mem8) > 0 and temp ? (mem8) > 7fh or temp ? (mem8) < 0 and temp ? (mem8) 0 C 7fh C1 ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta temp ? dw, aw if temp ? reg16 > 0 and temp ? reg16 7fffh or temp ? reg16 < 0 and temp ? reg16 > 0 C 7fffh C1 dw ? temp%reg16, aw ? temp ? reg16 if temp ? reg16 > 0 and temp ? reg16 > 7fffh or temp ? reg16 < 0 and temp ? reg16 0 C 7fffh C1 ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta temp ? dw, aw if temp ? (mem16) > 0 and temp ? (mem16) 7fffh or temp ? (mem16) < 0 and temp ? (mem16) > 0 C 7fffh C1 dw ? temp%(mem16), aw ? temp ? (mem16) if temp ? (mem16) > 0 and temp ? (mem16) > 7fffh or temp ? (mem16) < 0 and temp ? (mem16) 0 C 7fffh C1 ta ? (001h, 000h), tc ? (003h, 002h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 29-34 34-39 38-43 47-52 div signed division instructions clock cycles v40hl v50hl 29-34 34-39 38-43 43-48/ 47-52 49 m pd70208h, 70216h data sheet u13225ej4v0ds00 if al 0fh > 9 or ac = 1: al ? al + 6 ah ? ah + 1, ac ? 1, cy ? ac, al ? al 0fh if al 0fh > 9 or ac = 1 al ? al + 6, cy ? cy ac , ac ? 1 if al > 9fh or cy = 1 al ? al + 60h, cy ? 1 if al 0fh > 9 or ac = 1 al ? al C 6, ah ? ah C 1 , ac ? 1 cy ? ac, al ? al 0fh if al 0fh > 9 or ac = 1 al ? al C6, cy ? cy ac , ac ? 1 if al > 9fh or cy = 1 al ? al C 60h, cy ? 1 ah ? al ? 0ah, al ? al%0ah al ? ah 0ah + al, ah ? 0 if al < 80h: ah ? 0, otherwise: ah ? ffh if aw < 8000h: dw ? 0, otherwise: dw ? ffffh reg C reg (mem) C reg reg C (mem) reg C imm (mem) C imm if w = 0: al C imm if w = 1: aw C imm reg ? reg (mem) ? (mem) reg ? reg + 1 (mem) ? (mem) + 1 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 76543210 reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg mem reg mem 00110111 00100111 00111111 00101111 11010100 11010101 10011000 10011001 0011101w 0011100w 0011101w 100000sw 100000sw 0011110w 1111011w 1111011w 1111011w 1111011w 00001010 00001010 1 1 reg reg mod reg mem mod reg mem 11111 reg mod 111 mem 1 1 0 1 0 reg mod 0 1 0 mem 1 1 0 1 1 reg mod 0 1 mem 1 1 1 1 2 2 1 1 2 2-4 2-4 3-4 3-6 2-3 2 2-4 2 2-4 uuuu u uuuu u uuu uuu 7 3 7 3 15 7 2 4-5 2 10/14 10/14 4 12/16 4 2 13/21 2 13/21 adjba adj4a adjbs adj4s cvtbd cvtdb cvtbw cvtwl cmp not neg complement operation instructions comparison instructions bcd adjustment instructions data conversion instructions clock cycles v40hl v50hl 7 3 7 3 15 7 2 4-5 2 10/14 10/14 4 12/16 4 2 13/21 2 13/21 50 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) operation operation code flags 76543210 76543210 reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm reg, reg mem, reg reg, mem reg, imm mem, imm acc, imm 1000010w 1000010w 1111011w 1111011w 1010100w 0010001w 0010000w 0010001w 1000000w 1000000w 0010010w 0000101w 0000100w 0000101w 1000000w 1000000w 0000110w 0011001w 0011000w 0011001w 1000000w 1000000w 0011010w 1 1 reg reg mod reg mem 11000 reg mod 000 mem 1 1 reg reg mod reg mem mod reg mem 11100 reg mod 100 mem 1 1 reg reg mod reg mem mod reg mem 11001 reg mod 001 mem 1 1 reg reg mod reg mem mod reg mem 11110 reg mod 110 mem 2 2-4 3-4 3-6 2-3 2 2-4 2-4 3-4 3-6 2-3 2 2-4 2-4 3-4 3-6 2-3 2 2-4 2-4 3-4 3-6 2-3 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 u0 0 2 9/13 4 10/14 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 test and or xor logical operation instructions reg reg (mem) reg reg imm (mem) imm if w = 0: al imm8 if w = 1: aw imm16 reg ? reg reg (mem) ? (mem) reg reg ? reg (mem) reg ? reg imm (mem) ? (mem) imm if w = 0: al ? al imm8 if w = 1: aw ? aw imm16 reg ? reg reg (mem) ? (mem) reg reg ? reg (mem) reg ? reg imm (mem) ? (mem) imm if w = 0: al ? al imm8 if w = 1: aw ? aw imm16 reg ? reg reg (mem) ? (mem) reg reg ? reg (mem) reg ? reg imm (mem) ? (mem) imm if w = 0: al ? al imm8 if w = 1: aw ? aw imm16 bytes clock cycles v40hl v50hl 2 9/13 4 10/14 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 2 13/21 10/14 4 15/23 4 51 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) operation operation code flags 76543210 76543210 reg8, cl mem8, cl reg16, cl mem16, cl reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 reg8, cl mem8, cl reg16, cl mem16, cl reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 00010000 0000 0001 0001 1000 1000 1001 1001 0110 0110 0111 0111 1110 1110 1111 1111 11000 reg mod 000 mem 11000 mem mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 3 3-5 3 3-5 4 4-6 4 4-6 3 3-5 3 3-5 4 4-6 4 4-6 u0 0uu u0 0uu u0 0uu u0 0uu u0 0uu u0 0uu u0 0uu u0 0uu reg8 bit no.cl = 0 : z ? 1 reg8 bit no.cl = 1 : z ? 0 (mem8) bit no.cl = 0 : z ? 1 (mem8) bit no.cl = 1 : z ? 0 reg16 bit no.cl = 0 : z ? 1 reg16 bit no.cl = 1 : z ? 0 (mem16) bit no.cl = 0 : z ? 1 (mem16) bit no.cl = 1 : z ? 0 reg8 bit no.imm3 = 0 : z ? 1 reg8 bit no.imm3 = 1 : z ? 0 (mem8) bit no.imm3 = 0 : z ? 1 (mem8) bit no.imm3 = 1 : z ? 0 reg16 bit no.imm4 = 0 : z ? 1 reg16 bit no.imm4 = 1 : z ? 0 (mem16) bit no.imm4 = 0 : z ? 1 (mem16) bit no.imm4 = 1 : z ? 0 reg8 bit no.cl ? reg8 bit no.cl (mem8) bit no.cl ? (mem8) bit no.cl reg16 bit no.cl ? reg16 bit no.cl (mem16) bit no.cl ? (mem16) bit no.cl reg8 bit no.imm3 ? reg8 bit no.imm3 (mem8) bit no.imm3 ? (mem8) bit no.imm3 reg16 bit no.imm4 ? reg16 bit no.imm4 (mem16) bit no.imm4 ? (mem16) bit no.imm4 test1 not1 3 7 3 11 4 8 4 12 4 10 4 18 5 11 5 19 not1 cy 11110101 1 2 bit manipulation instructions 2nd byte * 3rd byte * * 1st byte = 0fh bytes clock cycles v40hl v50hl 3 7 3 7/11 4 8 4 8/12 4 10 4 10/18 5 11 5 11/19 cy ? cy 2 52 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) operation operation code flags 76543210 76543210 reg8, cl mem8, cl reg16, cl mem16, cl reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 reg8, cl mem8, cl reg16, cl mem16, cl reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 00010010 0010 0011 0011 1010 1010 1011 1011 0100 0100 0101 0101 1100 1100 1101 1101 11000 reg mod 000 mem 11000 mem mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem 3 3-5 3 3-5 4 4-6 4 4-6 3 3-5 3 3-5 4 4-6 4 4-6 reg8 bit no.cl ? 0 (mem8) bit no.cl ? 0 reg16 bit no.cl ? 0 (mem16) bit no.cl ? 0 reg8 bit no.imm3 ? 0 (mem8) bit no.imm3 ? 0 reg16 bit no.imm4 ? 0 (mem16) bit no.imm4 ? 0 reg8 bit no.cl ? 1 (mem8) bit no.cl ? 1 reg16 bit no.cl ? 1 (mem16) bit no.cl ? 1 reg8 bit no.imm3 ? 1 (mem8) bit no.imm3 ? 1 reg16 bit no.imm4 ? 1 (mem16) bit no.imm4 ? 1 clr1 set1 5 11 5 19 6 12 6 20 4 10 4 18 5 11 5 19 clr1 set1 cy dir cy dir 11111000 11111100 11111001 11111101 1 1 1 1 2 2 2 2 0 1 2nd byte * 3rd byte * * 1st byte = 0fh bit manipulation instructions bytes clock cycles v40hl v50hl 5 11 5 11/19 6 12 6 12/20 4 10 4 10/18 5 11 5 11/19 cy ? 0 dir ? 0 cy ? 1 dir ? 1 2 2 2 2 53 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z u u u u u u u u u u instruc- tion group shift instructions mnemonic operand(s) operation operation code flags 76543210 76543210 cy ? reg msb, reg ? reg 2 if reg msb 1 cy: v ? 1 if reg msb = cy: v ? 0 cy ? (mem) msb, (mem) ? (mem) 2 if (mem) msb 1 cy: v ? 1 if (mem) msb = cy: v ? 0 temp ? cl, while temp 1 0 the following operation are repeated: cy ? reg msb, reg ? reg 2 temp ? temp C 1 temp ? cl, while temp 1 0 the following operation are repeated: cy ? (mem) msb, (mem) ? (mem) 2 temp ? temp C 1 temp ? imm8, while temp 1 0 the following operations are repeated: cy ? reg msb, reg ? reg 2 temp ? temp C 1 temp ? imm8, while temp 1 0 the following operations are repeated: cy ? (mem) msb, (mem) ? (mem) 2 temp ? temp C 1 shl reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 11100 reg mod 100 mem 11100 reg mod 100 mem 11100 reg mod 100 mem 2 2-4 2 2-4 3 3-5 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n n: number of shifts bytes clock cycles v40hl v50hl 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n 54 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 2 2-4 2 2-4 3 3-5 76543210 cy ? reg lsb, reg ? reg ? 2 if reg msb 1 bit after reg msb : v ? 1 if reg msb = bit after reg msb : v ? 0 cy ? (mem) lsb, (mem) ? (mem) ? 2 if (mem) msb 1 bit after (mem) msb : v ? 1 if (mem) msb = bit after (mem) msb : v ? 0 temp ? cl, while temp 1 0 the following operations are repeated: cy ? reg lsb, reg ? reg ? 2 temp ? temp C 1 temp ? cl, while temp 1 0 the following operations are repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2 temp ? temp C 1 temp ? imm8, while temp 1 0 the following operations are repeated: cy ? reg lsb, reg ? reg ? 2 temp ? temp C 1 temp ? imm8, while temp 1 0 the following operations are repeated: cy ? (mem) lsb,(mem) ? (mem) ? 2 temp ? temp C 1 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n shr reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 11101 reg mod 101 mem 11101 reg mod 101 mem 11101 reg mod 101 mem u u u u u u u u u u clock cycles v40hl v50hl shift instructions n: number of shifts 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n 55 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 2 2-4 2 2-4 3 3-5 76543210 cy ? reg lsb, reg ? reg ? 2, v ? 0 msb of operand is unchanged. cy ? (mem) lsb,(mem) ? (mem) ? 2, v ? 0 msb of operand is unchanged. temp ? cl, while temp 1 0 the following operations are repeated: cy ? reg lsb, reg ? reg ? 2 temp ? temp C 1, msb of operand is unchanged. temp ? cl, while temp 1 0 the following operations are repeated: cy ? (mem) lsb, (mem) ? (mem) ? 2 temp ? temp C 1, msb of operand is unchanged. temp ? imm8, while temp 1 0 the following operations are repeated: cy ? reg lsb, reg ? reg ? 2 temp ? temp C 1, msb of operand is unchanged. temp ? imm8, while temp 1 0 the following operations are repeated: cy ? (mem) lsb,(mem) ? (mem) ? 2 temp ? temp C 1, msb of operand is unchanged. 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n shra reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 11111 reg mod 111 mem 11111 reg mod 111 mem 11111 reg mod 111 mem u 0 u 0 u u u u u u u u clock cycles v40hl v50hl 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n n: number of shifts 56 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 2 2-4 2 2-4 3 3-5 76543210 cy ? reg msb, reg ? reg 2 + cy reg msb 1 cy : v ? 1 reg msb = cy : v ? 0 cy ? (mem) msb, (mem) ? (mem) 2 + cy (mem) msb 1 cy : v ? 1 (mem) msb = cy : v ? 0 temp ? cl, while temp 1 0 the following operations are repeated: cy ? reg msb, reg ? reg 2 + cy temp ? temp C 1 temp ? cl, while temp 1 0 the following operations are repeated: cy ? (mem) msb, (mem) ? (mem) 2 + cy temp ? temp C 1 temp ? imm8, while temp 1 0 the following operations are repeated: cy ? reg msb, reg ? reg 2 + cy temp ? temp C 1 temp ? imm8, while temp 1 0 the following operations are repeated: cy ? (mem) msb, (mem) ? (mem) 2 + cy temp ? temp C 1 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n rol reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 11000 reg mod 000 mem 11000 reg mod 000 mem 11000 reg mod 000 mem u u u u clock cycles v40hl v50hl 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n rotate instructions n: number of shifts 57 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 2 2-4 2 2-4 3 3-5 76543210 cy ? reg lsb, reg ? reg ? 2 reg msb ? cy reg msb 1 bit after reg msb : v ? 1 reg msb = bit after reg msb : v ? 0 cy ? (mem) lsb, (mem) ? (mem) ? 2 (mem) msb ? cy (mem) msb 1 bit after (mem) msb : v ? 1 (mem) msb = bit after (mem) msb : v ? 0 temp ? cl, while cl 1 0 the following operations are repeated: cy ? reg lsb, reg ? reg ? 2 reg msb ? cy temp ? temp C 1 temp ? cl, while cl 1 0 the following operations are repeated: cy ? (mem) lsb,(mem) ? (mem) ? 2 (mem) msb ? cy temp ? temp C 1 temp ? imm8, while cl 1 0 the following operations are repeated: cy ? reg lsb,reg ? reg ? 2 reg msb ? cy temp ? temp C 1 temp ? imm8, while cl 1 0 the following operations are repeated: cy ? (mem) lsb,(mem) ? (mem) ? 2 (mem) msb ? cy temp ? temp C 1 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n ror reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 11001 reg mod 001 mem 11001 reg mod 001 mem 11001 reg mod 001 mem u u u u clock cycles v40hl v50hl 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n n: number of shifts rotate instructions 58 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 2 2-4 2 2-4 3 3-5 76543210 tmpcy ? cy, cy ? reg msb reg ? reg 2 + tmpcy reg msb 1 cy : v ? 1 reg msb = cy : v ? 0 tmpcy ? cy, cy ? (mem) msb (mem) ? (mem) 2 + tmpcy (mem) msb 1 cy : v ? 1 (mem) msb = cy : v ? 0 temp ? cl, while cl 1 0 the following operations are re- peated: tmpcy ? cy, cy ? reg msb reg ? reg 2 + tmpcy temp ? temp C 1 temp ? cl, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? (mem) msb (mem) ? (mem) 2 + tmpcy temp ? temp C 1 temp ? imm8, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? reg msb reg ? reg 2 + tmpcy temp ? temp C 1 temp ? imm8, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? (mem) msb (mem) ? (mem) 2 + tmpcy temp ? temp C 1 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n rotate instructions rolc reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 11010 reg mod 010 mem 11010 reg mod 010 mem 11010 reg mod 010 mem u u u u clock cycles v40hl v50hl 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n n: number of shifts 76543210 59 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 1101000w 1101000w 1101001w 1101001w 1100000w 1100000w 2 2-4 2 2-4 3 3-5 76543210 tmpcy ? cy, cy ? reg lsb reg ? reg ? 2 reg msb ? tmpcy reg msb 1 bit after reg msb : v ? 1 reg msb = bit after reg msb : v ? 0 tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) ? 2 (mem) msb ? tmpcy (mem) msb 1 bit after (mem) msb : v ? 1 (mem) msb = bit after (mem) msb : v ? 0 temp ? cl, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? reg lsb reg ? reg ? 2 reg msb ? tmpcy temp ? temp C 1 temp ? cl, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) ? 2 (mem) msb ? tmpcy temp ? temp C 1 temp ? imm8, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? reg lsb reg ? reg ? 2 reg msb ? tmpcy temp ? temp C 1 temp ? imm8, while cl 1 0 the following operations are repeated: tmpcy ? cy, cy ? (mem) lsb (mem) ? (mem) ? 2 (mem) msb ? tmpcy temp ? temp C 1 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n rotate instructions rorc reg, 1 mem, 1 reg, cl mem, cl reg, imm8 mem, imm8 11011 reg mod 011 mem 11011 reg mod 011 mem 11011 reg mod 011 mem u u u u clock cycles v40hl v50hl 6 13/21 7 + n 16/24 + n 7 + n 16/24 + n n: number of shifts 60 m pd70208h, 70216h data sheet u13225ej4v0ds00 sp ? sp C 2, (sp + 1, sp) ? pc pc ? pc + disp sp ? sp C 2, (sp + 1, sp) ? pc pc ? regptr16 ta ? (memptr16) sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta sp ? sp C 2, (sp + 1, sp) ? ps, ps ? seg sp ? sp C 2, (sp + 1, sp) ? pc, pc ? offset ta ? (memptr32),tb ? (memptr32 + 2) sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tb sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta pc ? (sp + 1, sp) sp ? sp + 2 pc ? (sp + 1, sp) sp ? sp + 2, sp ? sp + pop-value pc ? (sp + 1, sp) ps ? (sp + 3, sp + 2) ps ? sp + 4 pc ? (sp + 1, sp) ps ? (sp + 3, sp + 2) sp ? sp + 4, sp ? sp + pop-value ac cy v p s z instruc- tion group mnemonic operand(s) operation operation code flags 76543210 11101000 11111111 11111111 10011010 11111111 11000011 11000010 11001011 11001010 3 2 2-4 5 2-4 1 3 1 3 76543210 20 18 31 29 47 19 24 29 32 call ret near-proc regptr16 memptr16 far-proc memptr32 pop-value pop-value 11010 reg mod 010 mem mod 011 mem subroutine control instructions bytes clock cycles v40hl v50hl 16/20 14/18 23/31 21/29 31/47 15/19 20/24 21/29 24/32 61 m pd70208h, 70216h data sheet u13225ej4v0ds00 2-4 1 1 1 1 2 3 2-4 1 1 1 1 4 1 23 10 10 10 65 9 10 24 12 12 12 75 note 1 10 mem16 reg16 sreg psw r imm8 imm16 mem16 reg16 sreg psw r imm16, imm8 sp ? sp C 2 (sp + 1, sp) ? (mem16) sp ? sp C 2 (sp + 1, sp) ? reg16 sp ? sp C 2 (sp + 1, sp) ? sreg sp ? sp C 2 (sp + 1, sp) ? psw push registers on the stack sp ? sp C 2 (sp + 1, sp) ? imm8, sign of extension sp ? sp C 2 (sp + 1, sp) ? imm16 (mem16) ? (sp + 1, sp) sp ? sp + 2 reg16 ? (sp + 1, sp) sp ? sp + 2 sreg ? (sp + 1, sp) sp ? sp + 2 psw ? (sp + 1, sp) sp ? sp + 2 pop registers from the stack prepare new stack frame dispose of stack frame ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 76543210 stack manipulation instructions mod 110 mem mod 000 mem rrrrrr sreg : ss, ds0, ds1 11111111 01010 reg 000 sreg 110 10011100 01100000 011010 10 0 1 1 0 1 0 0 0 10001111 01011 reg 000 sreg 111 10011101 01100001 11001000 11001001 push prepare dispose pop clock cycles v40hl v50hl 15/23 6/10 6/10 6/10 33/65 5/9 6/10 16/24 8/12 8/12 8/12 43/75 note 2 6/10 notes 1. if imm8 = 0 16 if imm8 3 1 21 + 16 (imm8 C 1) 2. if imm8 = 0 12/16 if imm8 3 1 {17 + 8 (imm8 C 1)} / {21 + 16 (imm8 C 1)} 62 m pd70208h, 70216h data sheet u13225ej4v0ds00 br 3 2 2 2-4 5 2-4 13 12 11 23 15 34 near-label short-label regptr16 memptr16 far-label memptr32 pc ? pc+ dsip pc ? pc+ ext-disp8 pc ? regptr16 pc ? (memptr16) ps ? seg pc ? offset ps ? (memptr32 + 2) pc ? (memptr32) ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 76543210 11100 reg mod 100 mem mod 101 mem 11101001 11101011 11111111 11111111 11101010 11111111 clock cycles v40hl v50hl 13 12 11 19/23 15 26/34 branch instructions 63 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 01110000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11100000 1110 0001 1110 0010 1110 0011 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 76543210 if v = 1 pc ? pc + ext-disp8 if v = 0 pc ? pc + ext-disp8 if cy = 1 pc ? pc + ext-disp8 if cy = 0 pc ? pc + ext-disp8 if z = 1 pc ? pc + ext-disp8 if z = 0 pc ? pc + ext-disp8 if cy z = 1 pc ? pc + ext-disp8 if cy z = 0 pc ? pc + ext-disp8 if s = 1 pc ? pc + ext-disp8 if s = 0 pc ? pc + ext-disp8 if p = 1 pc ? pc + ext-disp8 if p = 0 pc ? pc + ext-disp8 if s v = 1 pc ? pc + ext-disp8 if s v = 0 pc ? pc + ext-disp8 if (s v) z = 1 pc ? pc + ext-disp8 if (s v) z = 0 pc ? pc + ext-disp8 cw = cw C 1 pc ? pc + ext-disp8 if z = 0 and cw 1 0 cw = cw C 1 pc ? pc + ext-disp8 if z = 1 and cw 1 0 cw = cw C 1 pc ? pc + ext-disp8 if cw 1 0 if cw = 0 pc ? pc + ext-disp8 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/5 14/5 13/5 13/5 conditional branch instructions bv bnv bc bl bnc bnl be bz bne bnz bnh bh bn bp bpe bpo blt bge ble bgt dbnzne dbnze dbnz bcwz short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label clock cycles note v40hl v50hl 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/4 14/5 14/5 13/5 13/5 note condition determination: true/false 64 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 11001100 11001101 11001110 11001111 00001111 01100010 1 2 1 1 3 2-4 76543210 ta ? (00dh, 00ch), tc ? (00fh, 00eh) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta ta ? (4 n + 1, 4n), tc ? (4n + 3, 4n + 2) n = imm8 sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta if v = 1 ta ? (011h, 010h), tc ? (013h, 012h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta pc ? (sp + 1, sp), ps ? (sp + 3, sp + 2), psw ? (sp + 5, sp + 4), sp ? sp + 6 ta ? (4 n + 1, 4n), tc ? (4n + 3, 4n + 2) n = imm8 sp ? sp C 2, (sp + 1, sp) ? psw, md ? 0 md is set to write enabled sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta if (mem32) > reg16 or (mem32 + 2) < reg16 ta ? (015h, 014h), tc ? (017h, 016h) sp ? sp C 2, (sp + 1, sp) ? psw, ie ? 0, brk ? 0 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta 50 50 note 1 39 50 note 3 interrupt instructions brk brkv reti brkem chkind 3 imm8 ( = 3) imm8 reg16, mem32 11111111 mod reg mem rrrrrr notes 1. when v = 1: 52 when v = 0: 3 2. when v = 1: 40/52 when v = 0: 3 3. when interrupt condition is established : 72 to 75 when interrupt condition is not established : 25 4. when interrupt condition is established : (52 to 55)/(72 to 75) when interrupt condition is not established : 17/25 clock cycles v40hl v50hl 38/50 38/50 note 2 27/39 38/50 note 4 65 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 11110100 10011011 11111010 11111011 11110000 11011 xxx 11011 xxx 0110011 x 0110011 x 10010000 001 sreg 110 1 1 1 1 1 2 2-4 2 2-4 1 1 76543210 cpu halt poll and wait n: number of times poll pin is sampled ie ? 0 ie ? 1 bus lock prefix no operation data bus ? (mem) no operation data bus ? (mem) no operation segment override prefix 2 2 + 5n 2 2 2 2 14 2 14 3 2 halt poll di ei buslock fpo1 fpo2 nop * fp-op fp-op, mem fp-op fp-op, mem 11 yyyz z z mod yyy mem 11 yyyz z z mod yyy mem clock cycles v40hl v50hl cpu control instructions ac cy v p s z instruc- tion group mnemonic operand(s) bytes operation operation code flags 76543210 11101101 11101101 2 3 76543210 pc ? (sp + 1, sp), ps ? (sp + 3, sp + 2), psw ? (sp + 5, sp + 4), sp ? sp + 6, md is set to write disabled ta ? (4n + 1, 4n), tc ? (4n + 3, 4n + 2) n = imm8 sp ? sp C 2, (sp + 1, sp) ? psw, md ? 1 sp ? sp C 2, (sp + 1, sp) ? ps, ps ? tc sp ? sp C 2, (sp + 1, sp) ? pc, pc ? ta 39 58 retem calln imm8 11111101 11101101 8080 rrrrrr * ds0:, ds1:, ps:, and ss:. 2 2 + 5n 2 2 2 2 10/14 2 10/14 3 2 clock cycles v40hl v50hl 27/39 38/58 66 m pd70208h, 70216h data sheet u13225ej4v0ds00 16. electrical specifications applied standard the electrical characteristics shown below are applied to devices other than the old models conforming to k mask. therefore, these characteristics are different from those conforming to the k mask. for the electrical characteristics of the k mask, consult nec. others in the table below means products conforming to the masks other than e, p, x, and m (but conforming to the l, f mask). 16.1 at 5 v operation operating range e, p, x, m mask model others m pd70208h, 70216h-10/12/16 v dd = 5 v 10% m pd70208h, 70216h-20 v dd = 5 v 5% absolute maximum ratings (t a = 25 c) cautions 1. do not directly connect the output pins of two or more ic products and do not directly connect the output pins to v dd or v cc and gnd. however, open-drain pins or open-collector pins may be connected directly. moreover, an external circuit whose timing is designed to avoid output collision can be connected to pins that go into a high-impedance state. 2. if even one of the above parameters exceeds the absolute maximum rating even momentarily, the quality of the program may be degraded. absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. use the program keeping all the parameters within these rated values. the standards and conditions shown in dc and ac characteristics below specify the range within which the normal operation of the product is guaranteed. parameter symbol test conditions rating unit supply voltage input voltage clock input voltage output voltage operating ambient temperature storage temperature v dd v i v k v o t a t stg C0.5 to +7.0 v C0.5 to v dd + 0.3 v C0.5 to v dd + 1.0 v C0.5 to v dd + 0.3 v C40 to +85 c C65 to +150 c v dd = 5 v 10% ( m pd70208h, 70216h-10/12/16) v dd = 5 v 5% ( m pd70208h, 70216h-20) 67 m pd70208h, 70216h data sheet u13225ej4v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 5 v 10% ( m pd70208h, 70216h-10/12/16), v dd = 5 v 5% ( m pd70208h, 70216h-20)) parameter symbol test conditions min. typ. max. unit input voltage high v ih e, p, x, m except reset 2.2 v dd +0.3 v masks reset 0.8 v dd v dd +0.3 others except reset, 2.2 v dd +0.3 intp1 to intp7 reset 0.8 v dd v dd +0.3 intp1 to intp7 2.4 v dd +0.3 input voltage low v il except reset C0.5 +0.8 v reset C0.5 0.2v dd clock input voltage high v kh 3.9 v dd +1.0 v clock input voltage low v kl C0.5 +0.6 v output voltage high v oh i oh = C2.5 ma 0.7 v dd v i oh = C100 m av dd C 0.4 output voltage low v ol except end/tc : i ol = 2.5 ma 0.4 v end/tc : i ol = 5.0 ma input leak current high i lih v i = v dd 10 m a input leak current low i lil except intp:v i = 0 v C10 m a intp input current low i lipl intp input:v i = 0 v C300 m a output leak current high i loh v o = v dd 10 m a output leak current low i lol v o = 0 v C10 m a latch leak current high i llh v i = 3.0 v C50 C300 m a latch leak current low i lll v i = 0.8 v 50 300 m a latch inversion current (l ? h) i ilh 400 m a latch inversion current (h ? l) i ill C400 m a supply current note i dd e, p, x, m on operation 5.5 f x 9.0 f x ma masks on standby (halt) 1.5 f x 2.5 f x on standby (stop) 50 m a others on operation 4.5 f x 6.0 f x ma on standby (halt) 1.5 f x 2.2 f x on standby (stop) 50 m a note the unit of constant values (1.5, 2.2, 2.5, 4.5, 5.5, 6.0 and 9.0) is ma/mhz. capacitance (t a = 25 ?c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz 10 pf input/output capacitance c io 0 v other than test pin. 15 pf 68 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac characteristics (1) m pd70208h, 70216h-10/12/16 (t a = e40 to +85 c, v dd = 5 v 10%) (1/3) min. max. min. max. min. max. external clock input cycle external clock input high-level width (v kh =3.0 v) external clock input low-level width (v kl =1.5 v) external clock input rise time (1.5 ? 3.0 v) external clock input fall time (3.0 ? 1.5 v) clock output cycle clock output high-level width (v oh =3.0 v) clock output low-level width (v ol =1.5 v) clock output rise time (1.5 ? 3.0 v) clock output fall time (3.0 ? 1.5 v) clkout delay time (vs. external clock) input rise time (except external clock) (0.8 ? 2.2 v) input fall time (except external clock) (2.2 ? 0.8 v) output rise time e, p, x, m masks (except clkout) (0.8 ? 2.2 v) others output fall time (except clkout) (2.2 ? 0.8 v) reset setup time (vs. clkout ) note 1 reset hold time (vs. clkout ) note 1 resout output delay time (vs. clkout ) ready inactive setup time (vs. clkout - ) ready inactive hold time (vs. clkout - ) ready active setup time (vs. clkout - ) ready active hold time (vs. clkout - ) nmi setup time (vs. clkout - ) poll setup time (vs. clkout - ) data setup time (vs. clkout ) data hold time (vs. clkout ) clkout ? address delay time note 2 clkout ? address hold time clkout ? ps delay time clkout ? ps float delay time address setup time (vs. astb ) clkout ? address float delay time note 3 clkout ? astb - delay time output pin load capacitance: c l = 100 pf m pd70208h-10 m pd70216h-10 m pd70208h-16 m pd70216h-16 m pd70208h-12 m pd70216h-12 notes 1. when reset with the minimum pulse width or when guaranteeing the resout output timing. 2. specifications also corresponding to the qs0, qs1, and buslock signals, and a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. 3. specifications also corresponding to the a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. unit symbol parameter t cyx 50 dc 40 dc 31.25 dc ns t xxh 19 14 12 ns t xxl 19 14 12 ns t xr 555ns t xf 555ns t cyk 100 dc 80 dc 62.5 dc ns t kkh 0.5t cyk C5 0.5t cyk C5 0.5t cyk C5 ns t kkl 0.5t cyk C5 0.5t cyk C5 0.5t cyk C5 ns t kr 555ns t kf 555ns t dxk 40 35 20 ns t ir 15 15 15 ns t if 10 10 10 ns t or 15 15 15 ns 10 10 10 ns t of 10 10 10 ns t sresk 20 20 20 ns t hkres 25 25 15 ns t dkres 550540530ns t srylk 15 10 7 ns t hkryl 20 15 15 ns t sryhk 15 10 7 ns t hkryh 20 20 15 ns t snmik 15 15 15 ns t spolk 20 20 20 ns t sdk 15 10 7 ns t hkd 555ns t dka 550540528ns t hka 555ns t dkp 550540530ns t fkp 550540530ns t sast t kkl C20 t kkl C10 t kkl C10 ns t fka t hka 50 t hka 40 t hka 30 ns t dksth 40 30 25 ns <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> 69 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. min. max. min. max. clkout - ? astb delay time astb high-level width astb ? address hold time clkout ? control 1 note 1 delay time clkout ? control 2 note 2 delay time address float ? rd delay time clkout ? rd delay time clkout ? rd - delay time rd - ? address delay time rd low-level width bufen - ? bufr/w delay time (read cycle) clkout ? data output delay time clkout ? data float delay time wr low-level width wr - ? bufen - or bufr/w (write cycle) clkout - ? bs delay time clkout ? bs - delay time hldrq setup time (vs. clkout ) clkout ? hldak delay time clkout - ? dmaak delay time clkout ? dmaak delay time (cascade mode) wr low-level width dma extended write (dma cycle) dma normal write rd , wr delay time (vs. dmaak ) dmaak - delay time (vs. rd - ) rd - delay time (vs. wr - ) tc output delay time (vs. clkout - ) tc off delay time (vs. clkout - ) tc low-level width tc pull-up delay time (vs. clkout - ) end setup time (vs. clkout - ) end low-level width dmarq setup time (vs. clkout - ) intpn low-level width r x d setup time (vs. scu internal clock ) (1) m pd70208h, 70216h-10/12/16 (t a = e40 to +85 c, v dd = 5 v 10%) (2/3) m pd70208h-10 m pd70216h-10 m pd70208h-16 m pd70216h-16 m pd70208h-12 m pd70216h-12 notes 1. mwr and iowr signals in dma cycle 2. mwr and iowr signals in cpu cycles and bufen, bufr/w, intak and refrq signals. 3. t kkh + 2t cyk C 10 (reference value when a 1.1-k w pull-up resistor is connected.) 4. t kkh + 2t cyk C 5 (reference value when a 1.1-k w pull-up resistor is connected.) symbol parameter unit output pin load capacitance: c l = 100 pf t dkstl 45 35 30 ns t stst t kkl C10 t kkl C10 t kkl C10 ns t hsta t kkh C20 t kkh C10 t kkh C10 ns t dkct1 560550540ns t dkct2 555545535ns t dafrl 000ns t dkrl 565550540ns t dkrh 560545535ns t drha t cyk C40 t cyk C20 t cyk C10 ns t rr 2t cyk C40 2t cyk C20 2t cyk C20 ns t dbect t kkl C20 t kkl C10 t kkl C10 ns t dkd 555540530ns t fkd 555540530ns t ww 2t cyk C40 2t cyk C20 2t cyk C20 ns t dwct t kkl C20 t kkl C10 t kkl C10 ns t dkbl 555540530ns t dkbh 555540530ns t shqk 15 10 7 ns t dkha 560550540ns t dkhda 555545535ns t dklda 580570555ns t ww1 2t cyk C40 2t cyk C20 2t cyk C20 ns t ww2 t cyk C40 t cyk C20 t cyk C15 ns t ddarw t kkh C30 t kkh C20 t kkh C15 ns t drhdah t kkl C30 t kkl C20 t kkl C15 ns t dwhrh 333ns t dktcl 55 45 35 ns t dktcf 55 45 35 ns t tctcl t cyk C15 t cyk C10 t cyk C10 ns t dktch note 3 note 4 note 4 ns t sedk 30 25 20 ns t ededl 80 65 50 ns t sdqk 30 20 15 ns t ipipl 80 80 80 ns t srx 500 500 500 ns <34> <35> <36> <37> <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> <67> <68> 70 m pd70208h, 70216h data sheet u13225ej4v0ds00 (1) m pd70208h, 70216h-10/12/16 (t a = e40 to +85 c, v dd = 5 v 10%) (3/3) t hrx 500 500 500 ns t dksr 100 100 100 ns t dtx 200 200 200 ns t sgk 40 40 40 ns t sgtk 40 40 40 ns t hkg 80 80 80 ns t htkg 40 40 40 ns t ggh 40 40 40 ns t ggl 40 40 40 ns t dkto 150 150 150 ns t dtkto 100 100 100 ns t dgto 90 90 90 ns t tkr 25 25 25 ns t tkf 25 25 25 ns t tktkh 45 40 30 ns t tktkl 45 40 30 ns t cytk 100 dc 80 dc 62.5 dc ns t ai 2t cyk C40 2t cyk C25 2t cyk C20 ns t drqhrh t kkl C30 t kkl C15 t kkl C10 ns t wresl 4t cyk 4t cyk 4t cyk ns min. max. min. max. min. max. r x d hold time (vs. scu internal clock ) clkout ? srdy delay time tout1 ? t x d delay time tctl2 setup time (vs. clkout ) tctl2 setup time (vs. tclk - ) tctl2 hold time (vs. clkout ) tctl2 hold time (vs. tclk - ) tctl2 high-level width tctl2 low-level width tout output delay time (vs. clkout ) tout output delay time (vs. tclk ) tout output delay time (vs. tctl2 ) tclk rise time tclk fall time tclk high-level width tclk low-level width tclk cycle access interval note 1 refrq - delay time (vs. mrd - ) note 2 reset pulse width note 3 unit symbol parameter m pd70208h-10 m pd70216h-10 m pd70208h-16 m pd70216h-16 m pd70208h-12 m pd70216h-12 output pin load capacitance: c l = 100 pf <69> <70> <71> <72> <73> <74> <75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86> <87> <88> notes 1. specification to guarantee read/write recovery time for i/o device. 2. specification to guarantee that refrq - is always later than mrd - . only guaranteed when the eref bit of the sctl register is 0. 3. when using internal clock generator by connecting a resonator to the x1 and x2 pins, the oscillation stabilization time must be added at power-on. because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. 71 m pd70208h, 70216h data sheet u13225ej4v0ds00 (2) m pd70208h, 70216h-20 (t a = e40 to +85 c, v dd = 5 v 5%) (1/3) min. max. external clock input cycle external clock input high-level width (v kh =3.0 v) external clock input low-level width (v kl =1.5 v) external clock input rise time (1.5 ? 3.0 v) external clock input fall time (3.0 ? 1.5 v) clock output cycle clock output high-level width (v oh =3.0 v) clock output low-level width (v ol =1.5 v) clock output rise time (1.5 ? 3.0 v) clock output fall time (3.0 ? 1.5 v) clkout delay time (vs. external clock) input rise time (except external clock) (0.8 ? 2.2 v) input fall time (except external clock) (2.2 ? 0.8 v) output rise time (except clkout) (0.8 ? 2.2 v) output fall time (except clkout) (2.2 ? 0.8 v) reset setup time (vs. clkout ) note 1 reset hold time (vs. clkout ) note 1 resout output delay time (vs. clkout ) ready inactive setup time (vs. clkout - ) ready inactive hold time (vs. clkout - ) ready active setup time (vs. clkout - ) ready active hold time (vs. clkout - ) nmi setup time (vs. clkout - ) poll setup time (vs. clkout - ) data setup time (vs. clkout ) data hold time (vs. clkout ) clkout ? address delay time note 2 clkout ? address hold time clkout ? ps delay time clkout ? ps float delay time address setup time (vs. astb ) clkout ? address float delay time note 3 clkout ? astb - delay time clkout - ? astb delay time astb high-level width output pin load capacitance: c l = 100 pf m pd70208h-20 m pd70216h-20 unit parameter symbol t cyx 25 dc ns t xxh 10 ns t xxl 10 ns t xr 5ns t xf 5ns t cyk 50 dc ns t kkh 0.5t cyk C5 ns t kkl 0.5t cyk C5 ns t kr 5ns t kf 5ns t dxk 20 ns t ir 15 ns t if 10 ns t or 10 ns t of 10 ns t sresk 20 ns t hkres 10 ns t dkres 525ns t srylk 7ns t hkryl 10 ns t sryhk 7ns t hkryh 10 ns t snmik 10 ns t spolk 20 ns t sdk 7ns t hkd 5ns t dka 525ns t hka 5ns t dkp 530ns t fkp 530ns t sast t kkl C10 ns t fka t hka 25 ns t dksth 20 ns t dkstl 20 ns t stst t kkl C10 ns <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> notes 1. when reset with the minimum pulse width or when guaranteeing the resout output timing. 2. specifications also corresponding to the qs0, qs1, and buslock signals, and a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. 3. specifications also corresponding to the a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. 72 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. astb ? address hold time clkout ? control 1 note 1 delay time clkout ? control 2 note 2 delay time address float ? rd delay time clkout ? rd delay time clkout ? rd - delay time rd - ? address delay time rd low-level width bufen - ? bufr/w delay time (read cycle) clkout ? data output delay time clkout ? data float delay time wr low-level width wr - ? bufen - or bufr/w (write cycle) clkout - ? bs delay time clkout ? bs - delay time hldrq setup time (vs. clkout ) clkout ? hldak delay time clkout - ? dmaak delay time clkout ? dmaak delay time (cascade mode) wr low-level width (dma cycle) dma extended write dma normal write rd , wr delay time (vs. dmaak ) dmaak - delay time (vs. rd - ) rd - delay time (vs. wr - ) tc output delay time (vs. clkout - ) tc off delay time (vs. clkout - ) tc low-level width tc pull-up delay time (vs. clkout - ) end setup time (vs. clkout - ) end low-level width dmarq setup time (vs. clkout - ) intpn low-level width rxd setup time (vs. scu internal clock ) rxd hold time (vs. scu internal clock ) clkout ? srdy delay time notes 1. mwr and iowr signals in dma cycle 2. mwr and iowr signals in bufen, bufr/w, intak, refrq, and cpu cycles 3. t kkh + 2t cyk C 5 (reference value when a 1.1-k w pull-up resistor is connected) (2) m pd70208h, 70216h-20 (t a = e40 to +85 c, v dd = 5 v 5%) (2/3) output pin load capacitance: c l = 100 pf m pd70208h-20 m pd70216h-20 unit parameter symbol t hsta t kkh C10 ns t dkct1 525ns t dkct2 530ns t dafrl 0ns t dkrl 525ns t dkrh 528ns t drha t cyk C5 ns t rr 2t cyk C15 ns t dbect t kkl C10 ns t dkd 525ns t fkd 525ns t ww 2t cyk C15 ns t dwct t kkl C10 ns t dkbl 530ns t dkbh 525ns t shqk 7ns t dkha 525ns t dkhda 525ns t dklda 545ns t ww1 2t cyk C15 ns t ww2 t cyk C15 ns t ddarw t kkh C10 ns t drhdah t kkl C10 ns t dwhrh 3ns t dktcl 25 ns t dktcf 25 ns t tctcl t cyk C10 ns t dktch note 3 ns t sedk 20 ns t ededl 40 ns t sdqk 10 ns t ipipl 60 ns t srx 500 ns t hrx 500 ns t dksr 100 ns <36> <37> <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> <67> <68> <69> <70> 73 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. tout1 ? txd delay time tctl2 setup time (vs. clkout ) tctl2 setup time (vs. tclk - ) tctl2 hold time (vs. clkout ) tctl2 hold time (vs. tclk - ) tctl2 high-level width tctl2 low-level width tout output delay time (vs. clkout ) tout output delay time (vs. tclk ) tout output delay time (vs. tctl2 ) tclk rise time tclk fall time tclk high-level width tclk low-level width tclk cycle access interval note 1 refrq - delay time (vs. mrd - ) note 2 reset pulse width note 3 (2) m pd70208h, 70216h-20 (t a = e40 to +85 c, v dd = 5 v 5%) (3/3) output pin load capacitance: c l = 100 pf m pd70208h-20 m pd70216h-20 unit parameter symbol notes 1. this rating is to guarantee the read/write recovery time for the i/o device. 2. this rating is to guarantee that refrq - is always behind mrd - , and guaranteed only when the eref bit of the stcl register is 0. 3. when using internal clock generator by connecting a resonator to the x1 and x2 pins, the oscillation stabilization time must be added at power-on. because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. t dtx 200 ns t sgk 40 ns t sgtk 40 ns t hkg 80 ns t htkg 40 ns t ggh 40 ns t ggl 40 ns t dkto 150 ns t dtkto 100 ns t dgto 90 ns t tkr 25 ns t tkf 25 ns t tktkh 23 ns t tktkl 23 ns t cytk 50 dc ns t ai 2t cyk C15 ns t drqhrh t kkl C10 ns t wresl 4t cyk ns <71> <72> <73> <74> <75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86> <87> <88> 74 m pd70208h, 70216h data sheet u13225ej4v0ds00 recommended oscillator the clock input circuits (1) and (2) shown below are recommended. (1) ceramic resonator connection (t a = C40 to +85 c, v dd = 5 v 10% ( m pd70208h, 70216h-10/12/16), v dd = 5 v 5% ( m pd70208h, 70216h-20)) cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed in dashed line. 3. for matching between v40hl, v50hl and resonator, the efficient evaluation should be carried out. 4. the values of the oscillator constants c1 and c2 depend on the characteristics of the resonator used. evaluate them with the resonator actually used. recommended constant frequency (f xx ) [mhz] product name 40 32 25 20 32 25 20 3 5 5 10 5 5 10 3 5 5 10 5 5 10 c1 [pf] c2 [pf] csa40.00mxz040 csa32.00mxz040 csa25.00mxz040 csa20.00mxz040 fcr32.0m2g fcr25.0m2g fcr20.0m2g murata mfg. co., ltd. tdk corp. manufacturer or x1 x2 c1 c2 x1 x2 external clock high-speed cmos inverter x1 x2 external clock high-speed cmos inverter open (2) external clock input caution the high-speed cmos inverter should be as close as possible to the x1 and x2 pins. 75 m pd70208h, 70216h data sheet u13225ej4v0ds00 16.2 at 3 v operation operating range e, p, x, m masks others m pd70208h, 70216h-10/12/16 v dd = 3 v 10% m pd70208h, 70216h-20 v dd = 3 v 10% absolute maximum ratings (t a = 25 c) parameter symbol test conditions rating unit supply voltage input voltage clock input voltage output voltage operating ambient temperature storage temperature v dd v i v k v o t a t stg C0.5 to +7.0 v C0.5 to v dd + 0.3 v C0.5 to v dd + 1.0 v C0.5 to v dd + 0.3 v C40 to +85 c C65 to +150 c v dd = 3 v 10% cautions 1. do not directly connect the output pins of two or more ic products and do not directly connect the output pins to v dd or v cc and gnd. however, open-drain pins or open-collector pins may be connected directly. moreover, an external circuit whose timing is designed to avoid output collision can be connected to pins that go into a high-impedance state. 2. if even one of the above parameters exceeds the absolute maximum rating even momentarily, the quality of the program may be degraded. absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. use the program keeping all the parameters within these rated values. the standards and conditions shown in dc and ac characteristics below specify the range within which the normal operation of the product is guaranteed. 76 m pd70208h, 70216h data sheet u13225ej4v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 3 v 10%) parameter symbol test conditions min. typ. max. unit input voltage high v ih except reset 0.7 v dd v dd +0.3 v reset 0.8 v dd v dd +0.3 input voltage low v il except reset C0.5 0.2 v dd v reset clock input voltage high v kh 0.8 v dd v dd +0.5 v clock input voltage low v kl C0.5 0.2 v dd v output voltage high v oh i oh = C2.5 ma 0.7 v dd v i oh = C100 m av dd C 0.4 output voltage low v ol except end/tc : i ol = 2.5 ma 0.4 v end/tc : i ol = 5.0 ma input leak current high i lih v i = v dd 10 m a input leak current low i lil v i = 0 v : except intp C10 m a intp input current low i lipl v i = 0 v : intp input C300 m a output leak current high i loh v o = v dd 10 m a output leak current low i lol v o = 0 v C10 m a latch leak current high i llh v i = 3.0 v C50 C300 m a latch leak current low i lll v i = 0.8 v 50 300 m a latch inversion current (l ? h) i ilh 400 m a latch inversion current (h ? l) i ill C400 m a supply current note i dd e, p, x, m on operation 3.0 f x 5.5 f x ma masks on standby (halt) 0.9 f x 1.5 f x on standby (stop) 30 m a others on operation 2.5 f x 4.0 f x ma on standby (halt) 0.9 f x 1.5 f x on standby (stop) 30 m a note the unit of constant values (0.9, 1.5, 2.5, 3.0, 4.0 and 5.5) is ma/mhz. capacitance (t a = 25?c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i f c = 1 mhz 10 pf input/output capacitance c io 0 v other than test pin. 15 pf 77 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac characteristics (1) m pd70208h, 70216h-10/12/16 (t a = e40 to +85 c, v dd = 3 v 10%) (1/3) min. max. min. max. min. max. external clock input cycle external clock input high-level width (v kh =0.8 v dd ) external clock input low-level width (v kl =0.2 v dd ) external clock input rise time (0.2 v dd ? 0.8 v dd ) external clock input fall time (0.8 v dd ? 0.2 v dd ) clock output cycle clock output high-level width (v oh =0.7 v dd ) clock output low-level width (v ol =0.2 v dd ) clock output rise time (0.2 v dd ? 0.7 v dd ) clock output fall time (0.7 v dd ? 0.2 v dd ) clkout delay time (vs. external clock) input rise time (except external clock) (0.2 v dd ? 0.7 v dd ) input fall time (except external clock) (0.7 v dd ? 0.2 v dd ) output rise time (except clkout) (0.2 v dd ? 0.7 v dd ) output fall time (except clkout) (0.7 v dd ? 0.2 v dd ) reset setup time (vs. clkout ) note 1 reset hold time (vs. clkout ) note 1 resout output delay time (vs. clkout ) ready inactive setup time (vs. clkout - ) ready inactive hold time (vs. clkout - ) ready active setup time (vs. clkout - ) ready active hold time (vs. clkout - ) nmi setup time (vs. clkout - ) poll setup time (vs. clkout - ) data setup time (vs. clkout ) data hold time (vs. clkout ) clkout ? address delay time note 2 clkout ? address hold time clkout ? ps delay time clkout ? ps float delay time address setup time (vs. astb ) clkout ? address float delay time note 3 clkout ? astb - delay time clkout - ? astb delay time astb high-level width output pin load capacitance: c l = 100 pf m pd70208h-10 m pd70216h-10 m pd70208h-16 m pd70216h-16 m pd70208h-12 m pd70216h-12 unit symbol parameter notes 1. when reset with the minimum pulse width or when guaranteeing the resout output timing. 2. specifications also corresponding to the qs0, qs1, and buslock signals, and a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. 3. specifications also corresponding to the a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. t cyx 100 dc 83 dc 62.5 dc ns t xxh 40 30 20 ns t xxl 40 30 20 ns t xr 10 10 10 ns t xf 10 10 10 ns t cyk 200 dc 166 dc 125 dc ns t kkh 0.5t cyk C7 0.5t cyk C7 0.5t cyk C7 ns t kkl 0.5t cyk C7 0.5t cyk C7 0.5t cyk C7 ns t kr 777ns t kf 777ns t dxk 75 65 55 ns t ir 20 20 20 ns t if 12 12 12 ns t or 20 20 20 ns t of 12 12 12 ns t sresk 25 25 25 ns t hkres 35 35 35 ns t dkres 580570560ns t srylk 20 20 15 ns t hkryl 30 30 25 ns t sryhk 20 20 15 ns t hkryh 30 30 25 ns t snmik 15 15 15 ns t spolk 20 20 20 ns t sdk 20 20 15 ns t hkd 555ns t dka 575565555ns t hka 555ns t dkp 580570560ns t fkp 580570560ns t sast t kkl C30 t kkl C30 t kkl C30 ns t fka 580570560ns t dksth 565555545ns t dkstl 570560550ns t stst t kkl C10 t kkl C10 t kkl C10 ns <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> 78 m pd70208h, 70216h data sheet u13225ej4v0ds00 (1) m pd70208h, 70216h-10/12/16 (t a = e40 to +85 c, v dd = 3 v 10%) (2/3) output pin load capacitance: c l = 100 pf min. max. min. max. min. max. astb ? address hold time clkout ? control 1 note 1 delay time clkout ? control 2 note 2 delay time address float ? rd delay time clkout ? rd delay time clkout ? rd - delay time rd - ? address delay time rd low-level width bufen - ? bufr/w delay time (read cycle) clkout ? data output delay time clkout ? data float delay time wr low-level width wr - ? bufen - or bufr/w (write cycle) clkout - ? bs delay time clkout ? bs - delay time hldrq setup time (vs. clkout ) clkout ? hldak delay time clkout - ? dmaak delay time clkout ? dmaak delay time (cascade mode) wr low-level width dma extended write (dma cycle) dma normal write rd wr delay time (vs. dmaak ) dmaak - delay time (vs. rd - ) rd - delay time (vs. wr - ) tc output delay time (vs. clkout - ) tc off delay time (vs. clkout - ) tc low-level width tc pull-up delay time (vs. clkout - ) end setup time (vs. clkout - ) end low-level width dmarq setup time (vs. clkout - ) intpn low-level width r x d setup time (vs. scu internal clock ) r x d hold time (vs. scu internal clock ) clkout ? srdy delay time m pd70208h-10 m pd70216h-10 m pd70208h-16 m pd70216h-16 unit parameter symbol m pd70208h-12 m pd70216h-12 notes 1. mwr and iowr signals in dma cycle 2. mwr and iowr signals in cpu cycles and bufen, bufr/w, intak and refrq signals. 3. t kkh + 2t cyk C 20 (reference value when a 1.1-k w pull-up resistor is connected) 4. t kkh + 2t cyk C 10 (reference value when a 1.1-k w pull-up resistor is connected) t hsta t kkh C30 t kkh C30 t kkh C20 ns t dkct1 590580570ns t dkct2 580570560ns t dafrl 000ns t dkrl 595585575ns t dkrh 590580570ns t drha t cyk C70 t cyk C60 t cyk C50 ns t rr 2t cyk C70 2t cyk C60 2t cyk C50 ns t dbect t kkl C30 t kkl C30 t kkl C20 ns t dkd 580570560ns t fkd 580570560ns t ww 2t cyk C50 2t cyk C50 2t cyk C40 ns t dwct t kkl C30 t kkl C30 t kkl C20 ns t dkbl 580570560ns t dkbh 580570560ns t shqk 25 25 20 ns t dkha 590580570ns t dkhda 580570560ns t dklda 5 110 5 100 5 90 ns t ww1 2t cyk C50 2t cyk C50 2t cyk C40 ns t ww2 t cyk C50 t cyk C50 t cyk C40 ns t ddarw t kkh C40 t kkh C40 t kkh C30 ns t drhdah t kkl C40 t kkl C40 t kkl C30 ns t dwhrh 555ns t dktcl 580570560ns t dktcf 580570560ns t tctcl t cyk C25 t cyk C25 t cyk C15 ns t dktch note 3 note 4 note 4 ns t sedk 45 40 35 ns t ededl 140 120 100 ns t sdqk 45 40 35 ns t ipipl 100 100 100 ns t srx 1000 1000 1000 ns t hrx 1000 1000 1000 ns t dksr 150 150 150 ns <36> <37> <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> <67> <68> <69> <70> 79 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. min. max. min. max. tout1 ? t x d delay time tctl2 setup time (vs. clkout ) tctl2 setup time (vs. tclk - ) tctl2 hold time (vs. clkout ) tctl2 hold time (vs. tclk - ) tctl2 high-level width tctl2 low-level width tout output delay time (vs. clkout ) tout output delay time (vs. tclk ) tout output delay time (vs. tctl2 ) tclk rise time tclk fall time tclk high-level width tclk low-level width tclk cycle access interval note 1 refrq - delay time (vs. mrd - ) note 2 reset pulse width note 3 (1) m pd70208h, 70216h-10/12/16 (t a = e40 to +85 c, v dd = 3 v 10%) (3/3) output pin load capacitance: c l = 100 pf m pd70208h-10 m pd70216h-10 unit parameter m pd70208h-12 m pd70216h-12 t dtx 500 500 500 ns t sgk 50 50 50 ns t sgtk 50 50 50 ns t hkg 100 100 100 ns t htkg 50 50 50 ns t ggh 50 50 50 ns t ggl 50 50 50 ns t dkto 200 200 200 ns t dtkto 150 150 150 ns t dgto 120 120 120 ns t tkr 25 25 25 ns t tkf 25 25 25 ns t tktkh 60 55 50 ns t tktkl 60 55 50 ns t cytk 200 dc 166 dc 125 dc ns t ai 2t cyk C70 2t cyk C60 2t cyk C50 ns t drqhrh t kkl C50 t kkl C40 t kkl C30 ns t wresl 4t cyk 4t cyk 4t cyk ns symbol m pd70208h-16 m pd70216h-16 notes 1. specification to guarantee read/write recovery time for i/o device. 2. specification to guarantee that refrq - is always later than mrd - . only guaranteed when the eref bit of the sctl register is 0. 3. when using internal clock generator by connecting a resonator to the x1 and x2 pins, the oscillation stabilization time must be added at power-on. because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. <71> <72> <73> <74> <75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86> <87> <88> 80 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. external clock input cycle external clock input high-level width (v kh =0.8 v dd ) external clock input low-level width (v kl =0.2 v dd ) external clock input rise time (0.2 v dd ? 0.8 v dd ) external clock input fall time (0.8 v dd ? 0.2 v dd ) clock output cycle clock output high-level width (v oh =0.7 v dd ) clock output low-level width (v ol =0.2 v dd ) clock output rise time (0.2 v dd ? 0.7 v dd ) clock output fall time (0.7 v dd ? 0.2 v dd ) clkout delay time (vs. external clock) input rise time (except external clock) (0.2 v dd ? 0.7 v dd ) input fall time (except external clock) (0.7 v dd ? 0.2 v dd ) output rise time (except clkout) (0.2 v dd ? 0.7 v dd ) output fall time (except clkout) (0.7 v dd ? 0.2 v dd ) reset setup time (vs. clkout ) note 1 reset hold time (vs. clkout ) note 1 resout output delay time (vs. clkout ) ready inactive setup time (vs. clkout - ) ready inactive hold time (vs. clkout - ) ready active setup time (vs. clkout - ) ready active hold time (vs. clkout - ) nmi setup time (vs. clkout - ) poll setup time (vs. clkout - ) data setup time (vs. clkout ) data hold time (vs. clkout ) clkout ? address delay time note 2 clkout ? address hold time clkout ? ps delay time clkout ? ps float delay time address setup time (vs. astb ) clkout ? address float delay time note 3 clkout ? astb - delay time clkout - ? astb delay time astb high-level width (2) m pd70208h, 70216h-20 (t a = e40 to +85 c, v dd = 3 v 10%) (1/3) output pin load capacitance: c l = 100 pf m pd70208h-20 m pd70216h-20 unit parameter symbol t cyx 50 dc ns t xxh 19 ns t xxl 19 ns t xr 5ns t xf 5ns t cyk 100 dc ns t kkh 0.5t cyk C7 ns t kkl 0.5t cyk C7 ns t kr 7ns t kf 7ns t dxk 45 ns t ir 15 ns t if 10 ns t or 15 ns t of 10 ns t sresk 25 ns t hkres 25 ns t dkres 550ns t srylk 15 ns t hkryl 20 ns t sryhk 15 ns t hkryh 20 ns t snmik 15 ns t spolk 20 ns t sdk 15 ns t hkd 5ns t dka 550ns t hka 5ns t dkp 550ns t fkp 550ns t sast t kkl C20 ns t fka t hka 50 ns t dksth 40 ns t dkstl 45 ns t stst t kkl C10 ns <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> notes 1. when reset with the minimum pulse width or when guaranteeing the resout output timing. 2. specifications also corresponding to the qs0, qs1, and buslock signals, and a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. 3. specifications also corresponding to the a16/ps0-a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr, and bs0-bs2 signals at hldrq/hldak timing. 81 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. astb ? address hold time clkout ? control 1 note 1 delay time clkout ? control 2 note 2 delay time address float ? rd delay time clkout ? rd delay time clkout ? rd - delay time rd - ? address delay time rd low-level width bufen - ? bufr/w delay time (read cycle) clkout ? data output delay time clkout ? data float delay time wr low-level width wr - ? bufen - or bufr/w (write cycle) clkout - ? bs delay time clkout ? bs - delay time hldrq setup time (vs. clkout ) clkout ? hldak delay time clkout - ? dmaak delay time clkout ? dmaak delay time (cascade mode) wr low-level width (dma cycle) dma extended write dma normal write rd , wr delay time (vs. dmaak ) dmaak - delay time (vs. rd - ) rd - delay time (vs. wr - ) tc output delay time (vs. clkout - ) tc off delay time (vs. clkout - ) tc low-level width tc pull-up delay time (vs. clkout - ) end setup time (vs. clkout - ) end low-level width dmarq setup time (vs. clkout - ) intpn low-level width rxd setup time (vs. scu internal clock ) rxd hold time (vs. scu internal clock ) clkout ? srdy delay time notes 1. mwr and iowr signals in dma cycle 2. mwr and iowr signals in cpu cycles and bufen, bufr/w, intak and refrq signals. 3. t kkh + 2t cyk C 10 (reference value when a 1.1-k w pull-up resistor is connected) (2) m pd70208h, 70216h-20 (t a = e40 to +85 c, v dd = 3 v 10%) (2/3) output pin load capacitance: c l = 100 pf m pd70208h-20 m pd70216h-20 unit parameter symbol t hsta t kkh C20 ns t dkct1 560ns t dkct2 555ns t dafrl 0ns t dkrl 565ns t dkrh 560ns t drha t cyk C40 ns t rr 2t cyk C40 ns t dbect t kkl C20 ns t dkd 555ns t fkd 555ns t ww 2t cyk C40 ns t dwct t kkl C20 ns t dkbl 555ns t dkbh 555ns t shqk 15 ns t dkha 560ns t dkhda 555ns t dklda 580ns t ww1 2t cyk C40 ns t ww2 t cyk C40 ns t ddarw t kkh C30 ns t drhdah t kkl C30 ns t dwhrh 3ns t dktcl 55 ns t dktcf 55 ns t tctcl t cyk C15 ns t dktch note 3 ns t sedk 30 ns t ededl 80 ns t sdqk 30 ns t ipipl 80 ns t srx 500 ns t hrx 500 ns t dksr 100 ns <36> <37> <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> <67> <68> <69> <70> 82 m pd70208h, 70216h data sheet u13225ej4v0ds00 min. max. tout1 ? txd delay time tctl2 setup time (vs. clkout ) tctl2 setup time (vs. tclk - ) tctl2 hold time (vs. clkout ) tctl2 hold time (vs. tclk - ) tctl2 high-level width tctl2 low-level width tout output delay time (vs. clkout ) tout output delay time (vs. tclk ) tout output delay time (vs. tctl2 ) tclk rise time tclk fall time tclk high-level width tclk low-level width tclk cycle access interval note 1 refrq - delay time (vs. mrd - ) note 2 reset pulse width note 3 (2) m pd70208h, 70216h-20 (t a = e40 to +85 c, v dd = 3 v 10%) (3/3) output pin load capacitance: c l = 100 pf m pd70208h-20 m pd70216h-20 unit parameter symbol notes 1. this rating is to guarantee the read/write recovery time for the i/o device. 2. this rating is to guarantee that refrq - is always behind mrd - , and is guaranteed only when the eref bit of the stcl register is 0. 3. when using internal clock generator by connecting a resonator to the x1 and x2 pins, the oscillation stabilization time must be added at power-on. because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. t dtx 200 ns t sgk 40 ns t sgtk 40 ns t hkg 80 ns t htkg 40 ns t ggh 40 ns t ggl 40 ns t dkto 150 ns t dtkto 100 ns t dgto 90 ns t tkr 25 ns t tkf 25 ns t tktkh 45 ns t tktkl 45 ns t cytk 100 dc ns t ai 2t cyk C40 ns t drqhrh t kkl C30 ns t wresl 4t cyk ns <71> <72> <73> <74> <75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86> <87> <88> 83 m pd70208h, 70216h data sheet u13225ej4v0ds00 recommended oscillator the clock input circuits (1) and (2) shown below are recommended. (1) ceramic resonator connection (t a = C40 to +85 c, v dd = 3 v 10% note ) recommended constant frequency (f xx ) [mhz] 20 16 12.5 10 20 16 10 10 15 C 30 C 30 C 10 15 C 10 15 C 30 C 30 C 10 15 C c1 [pf] c2 [pf] murata mfg. co., ltd. manufacturer product name csa20.00mxz040 note csa16.00mxz040 csa16.00mxw0c3 csa12.5mtz csa12.5mtw csa10.0mtz cst10.0mxw fcr20.0m2g fcr16.0m2g fcr10.0mc tdk corp. cautions 1. the oscillator should be as close as possible to the x1 and x2 pins. 2. no other signal lines should pass through the area enclosed in dashed line. 3. v40hl, v50hl and resonator matching requires careful evaluation. 4. the values of the oscillator constants c1 and c2 depend on the characteristics of the resonator used. evaluate them with the resonator actually used. or x1 x2 c1 c2 x1 x2 external clock high-speed cmos inverter x1 x2 external clock high-speed cmos inverter open note use the cas20.00mxz040 within the range of v dd = 2.9 to 3.3 v. (2) external clock input caution the high-speed cmos inverter should be as close as possible to the x1 and x2 pins. 84 m pd70208h, 70216h data sheet u13225ej4v0ds00 ac test input waveform (except x1 and x2) (at 5 v operation) ac test output test points (at 5 v operation) ac test input waveform (except x1 and x2) (at 3 v operation) ac test output waveform (at 3 v operation) load conditions caution if the load capacitance exceeds 100 pf due to the configuration of the circuit, the load capacitance of this device should be reduced to 100 pf or less by insertion of a buffer, etc. 2.4 v 0.4 v 2.2 v 0.8 v test points 2.2 v 0.8 v 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd test points dut c = 100pf l 2.2 v 0.8 v 2.2 v 0.8 v test points 0.8 v dd 0.4 v 0.7 v dd 0.2 v dd test points 0.7 v dd 0.2 v dd m pd70208h, 70216h 85 data sheet u13225ej4v0ds00 clock timing note variation range reset timing ready timing (2) ready timing (1) external clock (input) (x1) clkout (output) <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <11> clkout (output) reset (input) resout (output) note <16> <17> <18> <16> <18> <88> t1 t2 t3 t4 t1 clkout (output) ready (input) variation range variation range <21> <22> clkout (output) ready (input) variation range variation range t1 t2 t3 tw t4 note <19> <20> <21> <22> 86 m pd70208h, 70216h data sheet u13225ej4v0ds00 read timing note high-level signal is output in case of internal access. remark a dashed line indicates high impedance. clkout (output) a16/ps0- a19/ps3 (output) ad0-ad7 (i/o): v40hl ad0-ad15 (i/o): v50hl astb (output) bufen (output) bufr/w (output) mrd (output) iord (output) bs0-bs2 (output) t4 t1 t2 t3 t4 a16-a19 ps0-ps3 a0-a7 (output) a0-a15 (output) d0-d7(intput) d0-d15(intput) note note bus status < 27 >< 28 > < 27 > < 31 > < 27 > < 31 > < 25 > < 33 > < 35 > < 26 > < 34 > < 38 >< 39 > < 44 > < 38 > < 40 >< 41 > < 43 >< 42 > < 49 >< 50 > < 30 > a8-a15 (output): v40hl ube (output): v50hl < 36 > < 28 > < 32 > < 29 > < 38 > < 38 > : v40hl : v50hl : v40hl : v50hl m pd70208h, 70216h 87 data sheet u13225ej4v0ds00 write timing note high-level signal is output in case of internal access. remark a dashed line indicates high impedance. t4 t1 t2 t3 t4 clkout (output) a16/ps0- a19/ps3 (output) a8-a15 (output): v40hl ube (output): v50hl ad0-ad7 (i/o): v40hl ad0-ad15 (i/o): v50hl astb (output) bufen (output) bufr/w (output) mwr (output) iowr (output) bs0-bs2 (output) a16-a19 ps0-ps3 a0-a7 (output) a0-a15 (output) d0-d7 (output) d0-d15 (output) note note bus status < 27 >< 45 >< 46 > < 31 > < 28 > < 38 > < 36 > < 38 > < 48 > < 38 >< 38 > < 47 > < 49 > < 50 > < 38 > < 27> < 28 > < 27 > < 29 > < 35 > < 34 > < 33 > < 38 > < 31 > < 30 > : v40hl : v50hl : v40hl : v50hl 88 m pd70208h, 70216h data sheet u13225ej4v0ds00 status timing notes 1. mrd, iord, mwr, iowr (all output) 2. high-level signal is output in case of internal access. remark a dashed line indicates high impedance. clkout (output) a16/ps0- a19/ps3 (output) a8-a15 (output): v40hl ube (output): v50hl ad0-ad7 (i/o): v40hl ad0-ad15 (i/o): v50hl astb (output) bs0-bs2 (output) note 1 qs0, qs1 (output) t4 t1 t2 t3 t4 < 27 > < 28 > < 29 > < 30 > < 27 > < 27 >< 28 > < 25 > < 26 > < 42 > < 50 > < 49 > < 39 > < 41 > < 27 >< 40 > < 43 > note 2 a16-a19 ps0-ps3 a0-a7 (output) a0-a15 (output) d0-d7 (input) d0-d15 (input) bus status < 34 > < 33 > < 36 > < 32 > < 35 > < 31 > < 31 > : v40hl : v50hl : v40hl : v50hl m pd70208h, 70216h 89 data sheet u13225ej4v0ds00 interrupt acknowledge timing (v40hl) notes 1. slave address in case of interrupt from external m pd71059. invalid data in case of interrupt from internal icu. 2. data read as vector address in case of interrupt from external m pd71059. high impedance in case of interrupt from internal icu. * 3. low-level output in case of interrupt from external m pd71059. high-level output in case of interrupt from internal icu. remark a dashed line indicates high impedance. t1 t2 t3 t4 t1 clkout (output) ad0-ad7 (i/o) astb (output) intak (output) bufen (output) bufr/w (output) buslock (output) vector number note 3 note 3 note 2 note 1 t2 t3 ti a8-a15 (output) <38> <38> <27> <38> <27> <32> <32> <25> <26> note 1 90 m pd70208h, 70216h data sheet u13225ej4v0ds00 interrupt acknowledge timing (v50hl) notes 1. slave address in case of interrupt from external m pd71059. invalid data in case of interrupt from internal icu. 2. data read as vector address in case of interrupt from external m pd71059. high impedance in case of interrupt from internal icu. * 3. low-level output in case of interrupt from external m pd71059. high-level output in case of interrupt from internal icu. remark a dashed line indicates high impedance. t1 t2 t3 ti 3t4 t1 clkout (output) ad0-ad15 (i/o) astb (output) intak (output) bufen (output) bufr/w (output) buslock (output) vector number note 3 note 3 note 2 note 1 t2 t3 ti <27> <38> <38> <38> <25> <26> <27> <32> <32> m pd70208h, 70216h 91 data sheet u13225ej4v0ds00 hldrq/hldak timing (1) note a16/ps0 to a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr (all output): v40hl, v50hl a8-a15 (output): v40hl ad0-ad7 (input/output): v40hl ad0-ad15 (input/output) v50hl remark a dashed line indicates high impedance. hldrq/hldak timing (2) note a16/ps0 to a19/ps3, ube, bufen, bufr/w, mrd, iord, mwr, iowr (all output): v40hl, v50hl a8-a15 (output): v40hl ad0-ad7 (input/output): v40hl ad0-ad15 (input/output) v50hl remark a dashed line indicates high impedance. ti ti t4 t1 <51> clkout (output) hldrq (input) hldak (output) note bs0-bs2 (output) <32> <32> <52> <51> <52> <27> <27> ti ti ti ti t4 t1 t2 clkout (output) hldrq (input) hldak (output) note bs0-bs2 (output) variation range <6> or longer highest-priority refresh cycle or dma cycle highest-priority refresh cycle or dma cycle <51> <52> <27> <49> 92 m pd70208h, 70216h data sheet u13225ej4v0ds00 poll, nmi input timing buslock output timing access interval tn clkout (output) poll (input) nmi (input) <23> <24> clkout (output) buslock (output) <27> <27> mrd (output) iord (output) mwr (output) iowr (output) <86> <86> <86> <86> m pd70208h, 70216h 93 data sheet u13225ej4v0ds00 refresh timing (v40hl) remark a dashed line indicates high impedance. < 43 > clkout (output) a16/ps0- a19/ps3 (output) ad0-ad7 (i/o) astb (output) bufen (output) mrd (output) refrq (output) bs0-bs2 (output) t4 t1 t2 t3 t4 < 27 > < 28 > < 29 > < 27 > < 27 > < 28 > < 39 > < 40 > < 38 > < 38 > < 49 >< 50 > bs2 = 1, bs1 = 0, bs0 = 1 invalid < 33 > < 36 > < 34 > < 32 > < 41 > a8-a15 (output) refresh address refresh address < 35 > < 31 > 94 m pd70208h, 70216h data sheet u13225ej4v0ds00 refresh timing (v50hl) remark a dashed line indicates high impedance. clkout (output) a16/ps0- a19/ps3 (output) ube (output) ad0-ad15 (i/o) astb (output) bufen (output) mrd (output) refrq (output) bs0-bs2 (output) t4 t1 t2 t3 t4 < 27 > < 28 > < 29 > < 27 > < 27 > < 28 > < 39 > < 40 > < 38 > < 38 > < 49 >< 50 > invalid refresh address bs2 = 1, bs1 = 0, bs0 = 1 < 32 > < 33 > < 36 > < 34 > < 43 > < 41 > < 31 > < 35 > m pd70208h, 70216h 95 data sheet u13225ej4v0ds00 tcu timing (1) note applies to tout2 output. tcu timing (2) note applies to tout2 output. clkout (output) tctl2 (input) toutn (output) (n=1, 2) note <72> <74> <77> <72> <74> <76> <80> <78> tclk (input) tctl2 (input) toutn (output) (n=1, 2) <84> note <85> <83> <81> <82> <73> <75> <76> <77> <73> <75> <79> <80> 96 m pd70208h, 70216h data sheet u13225ej4v0ds00 scu timing rxd (input) tout1 (output) 16 cycles or 64 cycles 16 cycles or 64 cycles txd (output) clkout (output) srdy (output) <70> <71> <68> <69> m pd70208h, 70216h 97 data sheet u13225ej4v0ds00 dmau timing (1) note low-level signal is output in extended write mode. remark a dashed line indicates high impedance. clkout (output) bs0-bs2 (output) astb (output) a16/ps0- a19/ps3 (output) a8-a15 (output): v40hl ube (output): v50hl ad0-ad7 (i/o): v40hl ad0-ad15 (i/o): v50hl dmaak (output) mrd (output) iord (output) mwr (output) iowr (output) t4 t1 t2 t3 t4 < 49 >< 50 > < 27 > < 29 > < 28 > < 27 > < 27 >< 28 > < 53 > < 53 > < 39 > < 40 > < 41 > < 58 > < 37 > < 37 > < 37 > < 59 > < 56 > < 55 > bus status < 57 > < 43 > note < 57 > < 33 > < 36 > < 34 > < 32 > < 35 > 98 m pd70208h, 70216h data sheet u13225ej4v0ds00 dmau timing (2) t1 t2 t3 t4 clkout (output) tc (input/output) end (input/output) clkout (output) dmarqn (input) (n=0-3) <66> <60> <61> <62> <63> <64> <65> m pd70208h, 70216h 99 data sheet u13225ej4v0ds00 dmau timing (3) (cascade mode) in normal operation: when refresh cycle is inserted: icu timing clkout (output) dmarq (input) dmaak (output) t1 t4 <54> <54> <66> <66> clkout (output) dmarq (input) dmaak (output) <54> <54> intpn (input) (n=1-7) <67> 100 m pd70208h, 70216h data sheet u13225ej4v0ds00 17. package drawings 80 pin plastic qfp (14x20) detail of lead end m f g h i j k m l n p q r item millimeters inches s p80gf-80-3b9-4 3.0 max. 0.119 max. k 1.8?.2 0.071 +0.008 ?.009 l 0.8?.2 0.031 +0.009 ?.008 n 0.10 0.004 m 0.17 0.007 +0.003 ?.004 q 0.1?.1 0.004?.004 a 23.6?.4 0.929?.016 b 20.0?.2 0.795 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 g f 0.8 1.0 0.031 0.039 d 17.6?.4 0.693?.016 j 0.8 (t.p.) 0.031 (t.p.) i 0.15 0.006 h 0.37 0.015 +0.003 ?.004 +0.08 ?.07 r5 ? 5 ? p 2.7?.1 0.106 +0.005 ?.004 +0.08 ?.07 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 64 65 40 80 1 25 24 41 s s a b cd s m pd70208h, 70216h 101 data sheet u13225ej4v0ds00 s80gk-50-9eu note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. item millimeters inches a b c d f g h i j k 14.0?.2 12.0?.2 1.25 0.22?.05 0.10 12.0?.2 l m 0.10 0.145?.05 1.0?.2 0.5 (t.p.) 0.5?.2 n 1.0?.05 14.0?.2 1.25 p 0.551?.008 0.472 0.551?.008 0.049 0.049 0.009 0.004 0.020 (t.p.) 0.039 0.020 0.006 0.004 0.040 +0.002 ?.003 0.472 +0.008 ?.009 q 0.1?.05 0.004?.002 s 1.2 max. 0.048 max. +0.002 ?.003 +0.009 ?.008 +0.009 ?.008 +0.009 ?.008 +0.002 ?.003 r3 3 +7 ? +7 ? 80 pin plastic tqfp (fine pitch) ( 12) b 60 a 41 40 21 61 80 120 c d g j h i m f n p k l m s r q detail of lead end 102 m pd70208h, 70216h data sheet u13225ej4v0ds00 68 1 + 0.08 - 0.07 s a b cd h m p j i g u t k e f item millimeters inches b 24.20 0.1 0.953 d 25.2 0.2 0.992 0.008 e 1.94 0.15 0.076 + 0.007 - 0.006 f 0.6 0.024 a 25.2 0.2 0.992 0.008 c 24.20 0.1 0.953 + 0.004 - 0.005 g 4.4 0.2 0.173 h 2.8 0.2 0.110 i 0.9 min. 0.035 min. j 3.4 0.1 0.134 k 1.27 (t.p.) 0.050 (t.p.) m 0.42 0.08 0.017 n 0.12 0.005 q 0.15 0.006 t r 0.8 r 0.031 u 0.22 0.009 + 0.004 - 0.005 + 0.009 - 0.008 + 0.009 - 0.008 + 0.004 - 0.005 + 0.003 - 0.004 + 0.003 - 0.004 s m p68l-50a1-3 q n notes 1. controlling dimension millimeter. 2. each lead centerline is located within 0.12 mm of its true position (t.p.) at maximum material condition. 68 pin plastic qfj (950 x 950 mil) p 23.12 0.2 0.910 + 0.009 - 0.008 m pd70208h, 70216h 103 data sheet u13225ej4v0ds00 18. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for the details of recommended soldering conditions for the surface mounting type, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact our salesman. table 18-1. soldering conditions (1) m pd70208hgf- -3b9 : 80-pin plastic qfp (14 20 mm) m pd70216hgf- -3b9 : 80-pin plastic qfp (14 20 mm) (a) k, e, x masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature : 230 c, time: 30 sec. max. (210 c min.), ir30-107-1 number of times: 1, number of days note : 7 days (after this, prebaking is necessary at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 sec. max. (200 c min.), vp15-107-1 number of times: 1, number of days note : 7 days (after this, prebaking is necessary at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max. time: 10 sec. max., number of times: 1, ws60-107-1 preheating temperature: 120 c max. (package surface temperature), number of days note : 7 days (after this, prebaking is necessary at 125 c for 10 hours). partial pin heating pin temperature: 300 c max., time: 3 sec. max. (per device side) (b) p, m masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (210 c min.), ir35-207-2 number of times: 2 max., number of days note : 7 days (after this, prebaking is necessary at 125 c for 20 hours). vps package peak temperature: 215 c, time: 40 sec. (200 c min.) vp15-207-2 number of times: 2 max., number of days note : 7 days (after this prebaking is necessary at 125 c for 20 hours). wave soldering solder bath temperature: 260 c max., time: 10 sec. max., ws60-207-1 number of times: 1, preheating temperature: 120 c max. (package surface temperature). number of days note : 7 days (after this, prebaking is necessary at 125 c for 20 hours). partial pin heating pin temperature: 300 c max., time: 3 sec. max. (per device side) note this means the number of days after unpacking the dry pack. storage conditions are 25 c and 65% rh max. 104 m pd70208h, 70216h data sheet u13225ej4v0ds00 (c) l, f masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (210 ?c min.), ir35-00-3 number of times: 3 max. vps package peak temperature: 215 c, time: 40 sec. (200 c min.) vp15-00-3 number of times: 3 max. wave soldering solder bath temperature: 260 c max., time: 10 sec. max., ws60-00-1 number of times: 1, preheating temperature: 120 c max. (package surface temperature) partial pin heating pin temperature: 300 c max., time: 3 sec. max. (per device side) caution do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods). m pd70208h, 70216h 105 data sheet u13225ej4v0ds00 (2) m pd70208hgk- -9eu : 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd70216hgk- -9eu : 80-pin plastic tqfp (fine pitch) (12 12 mm) (a) k, e, x masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature : 230 c, time: 30 sec. max. (210 c min.), ir30-101-1 number of timers: 1, number of days note : 1 day (after this, prebaking is necessary at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 sec. max. (200 c min.), vp15-101-1 number of times: 1, number of days note : 1 day (after this, prebaking is necessary at 125 c for 10 hours) partial pin heating pin temperature: 300 c max., time: 3 sec. max. (per device side) (b) p, m, l, f masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (210 c min.), ir35-107-2 number of times: 2 max., number of days note : 7 days (after this, prebaking is necessary at 125 c for 10 hours). vps package peak temperature: 215 c, time: 40 sec. (200 c min.), number of times: vp15-107-2 2 max., number of days note : 7 days (after this prebaking is necessary at 125 c for 10 hours). partial heating pin temperature: 300 c max., time: 3 sec. max. (per device side) note this means the number of days after unpacking the dry pack. storage conditions are 25 c and 65% rh max. caution do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods). 106 m pd70208h, 70216h data sheet u13225ej4v0ds00 (3) m pd70208hlp- : 68-pin plastic qfj (950 950 mil) m pd70216hlp- : 68-pin plastic qfj (950 950 mil) (a) k, e, x masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature : 230 c, time: 30 sec. max. (210 c min.), ir30-367-1 number of timers: 1, number of days note : 7 days (after this, prebaking is necessary at 125 c for 36 hours) vps package peak temperature: 215 c, time: 40 sec. max. (200 c min.), vp15-367-1 number of times: 1, number of days note : 7 days (after this, prebaking is necessary at 125 c for 36 hours) partial pin heating pin temperature: 300 c max., time: 3 sec. max. (per device side) (b) p, m, l, f masks soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (210 ?c min.), ir35-367-3 number of times: 3 max., number of days note : 7 days (after this, prebaking is necessary at 125 c for 36 hours). vps package peak temperature: 215 c, time: 40 sec. (200 c min.), vp15-367-3 number of times: 3 max., number of days note : 7 days (after this prebaking is necessary at 125 c for 36 hours). partial pin heating pin temperature: 300 c max., time: 3 sec. max. (per device side) note this means the number of days after unpacking the dry pack. storage conditions are 25 c and 65% rh max. caution do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods). m pd70208h, 70216h 107 data sheet u13225ej4v0ds00 [memo] 108 m pd70208h, 70216h data sheet u13225ej4v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd70208h, 70216h 109 data sheet u13225ej4v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1 [memo] v20, v20hl, v30, v30hl, v40, v40hl, v50, v50hl and v series are trademarks of nec corporation. m pd70208h, 70216h the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 |
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